ISO7240CFDW datasheet(24/46 Pages) TI1

24 / 46 page

ISO7240CF, ISO7240C, ISO7240M

ISO7241C, ISO7241M, ISO7242C, ISO7242M

SLLS868R – SEPTEMBER 2007 – REVISED SEPTEMBER 2015

www.ti.com

9.3 Feature Description

ISO724x are available in multiple channel configurations and default output state options to enable wide variety

of application uses.

SIGNALING

INPUT

CHANNEL

PRODUCT

RATE

THRESHOLD

CONFIGURATION

ISO7240C

25 Mbps

~1.5 V (TTL)

ISO7240CF

25 Mbps

~1.5 V (TTL)

4/0

ISO7240M

150 Mbps

VCC/ 2 (CMOS)

ISO7241C

25 Mbps

~1.5 V (TTL)

3/1

ISO7241M

150 Mbps

VCC/ 2 (CMOS)

ISO7242C

25 Mbps

~1.5 V (TTL)

2/2

ISO7242M

150 Mbps

VCC/ 2 (CMOS)

9.3.1 DIN V VDE V 0884-10 (VDE V 0884-10):2006-1 Insulation Characteristics(1)

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SPECIFICATIONS

UNIT

VIORM

Maximum working insulation voltage

560

VPK

After Input/Output Safety Test Subgroup 2/3

VPR = VIORM × 1.2, t = 10 s,

672

VPK

Partial discharge < 5 pC

Method a, VPR = VIORM × 1.6,

VPR

Input to output test voltage

Type and sample test with t = 10 s,

896

VPK

Partial discharge < 5 pC

Method b1, VPR = VIORM × 1.875,

100 % Production test with t = 1 s,

1050

VPK

Partial discharge < 5 pC

VIOTM

Maximum transient isolation voltage

t = 60 s

4000

VPK

Insulation resistance

VIO = 500 V at TS = 150°C

Ω

>109

Pollution degree

(1)

Climatic Classification 40/125/21

Table 1. IEC 60664-1 Ratings Table

PARAMETER

TEST CONDITIONS

SPECIFICATION

Basic isolation group

Material group

Rated mains voltage

≤150 VRMS

I-IV

Installation classification

Rated mains voltage

≤300 VRMS

I-III

9.3.2 Package Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Minimum air gap

L(I01)

Shortest pin-to-pin distance through air

(Clearance)(1)

Minimum external tracking

L(I02)

Shortest pin-to-pin distance across the package surface

(Creepage)(1)

Tracking resistance

CTI

DIN EN 60112 (VDE 0303-11); IEC 60112

≥ 400

(comparative tracking index)

Minimum Internal Gap

Distance through the insulation

0.008

(Internal Clearance)

Input to output, VIO = 500 V, all pins on each side of the

RIO

Isolation resistance

> 1012

Ω

barrier tied together creating a two-terminal device

CIO

Barrier capacitance Input to output

VI = 0.4 sin (4E6πt)

(1)

Per JEDEC package dimensions

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Product Folder Links: ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M

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