SN74LVC14ADBLE datasheet(14/35 Pages) TI1

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Vcc

Unused Input

Input

Output

Input

Unused Input

Output

SN54LVC14A, SN74LVC14A

SCAS285AA – MARCH 1993 – REVISED JUNE 2015

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11 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the

table.

Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single

supply, a 0.1-

μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μF

capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dual

supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended

for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors

with values of 0.1

μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close

to the power terminal as possible for best results.

12 Layout

12.1 Layout Guidelines

When using multiple-bit logic devices, inputs must never float.

In many cases, functions (or parts of functions) of digital logic devices are unused, for example, when only two

inputs of a triple-input AND gate are used or when only 3 of the 4 buffer gates are used. Such input pins must

not be left unconnected, because the undefined voltages at the outside connections result in undefined

operational states. Figure 7 specifies the rules that must be observed under all circumstances. All unused inputs

of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that

must be applied to any particular unused input depends on the function of the device. Generally they are tied to

GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,

unless the part is a transceiver. If the transceiver has an output enable pin, it disables the output section of the

part when asserted, which does not disable the input section of the I/Os. Therefore, the I/Os cannot float when

disabled.

12.2 Layout Examples

Figure 7. Layout Diagrams

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SN74LVC14ADBLE Datasheet(PDF) 14 Page - Texas Instruments