TABLE II

Select Code

Polynomial

0

0

0

0

0

100

C

1

1

1

1

1

0

1

Ethernet

D

1

1

1

1

1

0

1

Polynomial

E

0

0

0

0

0

0

0

Ethernet

F

0

0

0

0

0

1

0

Residue

7

1

1

1

1

1

0

0

CRC-16

B

1

1

1

1

1

0

0

CRC-CCITT

3

1

1

1

1

100

2

1

1

1

1

1

0

0

56th

4

1

1

1

1

1

0

0

Order

8

0

0

1

1

100

5

1

1

1

1

100

48th

9

1

1

1

1

100

Order

1

1

1

1

1

100

6

1

1

1

1

1

0

0

32nd

A

1

1

1

1

1

0

0

Order

Applications

In addition to polynomial selection there are four other ca-

pabilities provided for in the ’F402 ROM The first is set or

clear selectability The sixteen internal registers have the

capability to be either set or cleared when P is brought

LOW This set or clear capability is done in four groups of 4

determining the polarity of the check word As is the case

with the Ethernet polynomial the check word can be invert-

ed when it is appended to the data stream or as is the case

with the other polynomials the residue is appended with no

to select the RFB input instead of the SEI input to be fed

into the LSB This is used when the polynomial selected is

actually a residue (least significant) stored in the ROM

which indicates whether the selected location is a polynomi-

al or a residue If the latter then it inhibits the RFB input

As mentioned previously upon a successful data transmis-

sion the CRC register has a zero residue There is an ex-

ception to this however with respect to the Ethernet poly-

nomial This polynomial upon a successful data transmis-

sion has a non-zero residue in the CRC register (C7 04 DD

locations have been preloaded with the residue so that by

selecting these locations and clocking the device one addi-

tional time after the last check bit has been entered will

result in zeroing the CRC register In this manner a no-error

indication is achieved

requiring just one device In order to accommodate multi-

lower order polynomials a location of all zeros is provided

This allows the user to choose a lower order polynomial

even if the system is configured for a higher order one

The ’F402 expandable CRC generator checker contains 6

The application diagram

Also shown are the input patterns for other polynomials

When the ’F402 is used with a gated clock disabling the

clock in a HIGH state will ensure no erroneous clocking

occurs when the clock is re-enabled Preset and Master Re-

set are asynchronous inputs presetting the register to S or

Order select code 8 LSB are exceptions to this)

To generate a CRC the pattern for the selected polynomial

is applied to the S inputs the register is preset or cleared as

required clock is enabled CWG is set HIGH data is applied

to D input output data is on DCW When the last data bit

has been entered CWG is set LOW and the register is

clocked for n bits (where n is the order of the polynomial)

The clock may now be stopped if desired (holding CWG

LOW and clocking the register will output zeros from DCW

after the residue has been shifted out)

To check a CRC the pattern for the selected polynomial is

applied to the S inputs the register is preset or cleared as

required clock is enabled CWG is set HIGH the data

stream including the CRC is applied to D input When the

last bit of the CRC has been entered the ER output is

clock may now be stopped if desired

the number of packages required for the order of polynomial

and apply the pattern for the selected polynomial to the S

inputs (0000 on S inputs disables the package from the

feedback chain)

4