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UT699CPC Datasheet(PDF) 26 Page - Aeroflex Circuit Technology |
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UT699CPC Datasheet(HTML) 26 Page - Aeroflex Circuit Technology |
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26 / 41 page ![]() 26 Figure 5. Memory Interface, ERROR, and WDOG Output Timing Diagram 4.3 Input Timing Characteristics for Memory Interface (VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40 oC to 105oC) Notes: 1. CB[7] is not used for EDAC and is not tested 2. Guaranteed by design. . Figure 6. Memory Interface Input Timing Diagram Symbol Description Min Max Units t51 Setup time to SDCLK (DATA[31:0], CB[6:0], BEXC, and synchronous BRDY) 0- ns t61 Hold time from SDCLK (DATA[31:0], CB[6:0], BEXC, and synchronous BRDY) 1- ns t72 Asynchronous BRDY pulse width 1.5 - tCLK t4 t8 t3 t2 t1 t9 t9 SDCLK All Outputs DATA[31:0] and CB[7:0] ERROR and WDOG (Except Bi-Directs and Open-Drains) WRITE and RWE[3:0] (Bi-Direct Outputs) (Open-Drain Outputs) t6 t5 t7 t7 SDCLK All Inputs Asynchronous BRDY (Except Async BRDY) |
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