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UT54ACTS163 Datasheet(PDF) 2 Page - Aeroflex Circuit Technology |
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UT54ACTS163 Datasheet(HTML) 2 Page - Aeroflex Circuit Technology |
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2 / 10 page ![]() 2 FUNCTION TABLE H = High voltage level h = High voltage level one setup time prior to the low-to-high clock transition L = Low voltage level l = Low voltage level one setup time prior to the low-to-high clock transition Notes: 1. The RCO output is high when ENT is high and the counter is at terminal count HHHH. 2. The high-to-low transition of ENP or ENT should only occur while CLK is high for conventional operations. 3. The low-to-high transition of LOAD or CLR should only occur while CLK is high for conventional operations. LOGIC DIAGRAM Operating Mode CLR CLK ENP ENT LOAD DATA A,B,C,D QN RCO Reset (Clear) l ↑ X X X X L L Parallel Load h3 h3 ↑ ↑ X X X X l l l h L H L 1 Count h3 ↑ h h h X Count 1 Inhibit h3 h3 X X l 2 X X l 2 h3 h3 X X QN QN 1 L (2) (1) (9) (7) (10) (3) (4) (5) (6) (14) (12) (13) (11) (15) QA QB QC QD RCO DATA D DATA C DATA B DATA A ENT ENP LOAD CLR CLK C D Q Q C D Q Q C D Q Q C D Q Q |
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