UT8R128K32 datasheet(2/22 Pages) AEROFLEX

2 / 22 page

PIN NAMES

DEVICE OPERATION

The UT8R128K32 has six control inputs called Chip Enable 1

(E1), Chip Enable 2 (E2), Write Enable (W), Half-word Enables

(HHWE/LHWE) and Output Enable (G); 17 address inputs,

A(16:0); and 32 bidirectional data lines, DQ(15:0). E1 and E2

chip enables control device selection, active, or standby modes.

Asserting E1 and E2 enables the device, causes IDD to rise to its

active value, and decodes the 17 address inputs to select one of

131,072 words in the memory. W controls read and write

operations. During a read cycle, G must be asserted to enable

the outputs.

Table 1. Device Operation Truth Table

Notes:

1. “X” is defined as a “don’t care” condition.

2. Device active; outputs disabled.

A(16:0)

Address

Write Enable

DQ(31:0)

Data Input/Output

Output Enable

Chip Enable 1

(Active Low)

VDD1

Power (1.8V)

Chip Enable 2

(Active High)

VDD2

Power (3.3V)

HHWE

LWHE

High half-word enable

Low half-word enable

VSS

Ground

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Top View

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

VSS

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

VSS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

Figure 2. 15ns SRAM Pinout (68)

68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52

LHWE

HHWE

I/O Mode

Mode

DQ(31:16)

3-State

DQ(15:0)

3-State

Standby

DQ(31:16)

3-State

DQ(15:0)

3-State

Standby

DQ(31:16)

3-State

DQ(15:0)

Data Out

Low Half-Word

Read

DQ(31:16)

Data Out

DQ(15:0)

3-State

High Half-Word

Read

DQ(31:16)

Data Out

DQ(15:0)

Data Out

Word Read

DQ(31:16)

Data In

DQ(15:0)

Data In

Word Write

DQ(31:16)

3-State

DQ(15:0)

Data In

Low Half-Word

Write

DQ(31:16)

Data In

DQ(15:0)

3-State

High Half-Word

Write

DQ(31:16)

DQ(15:0)

All 3-State

3-State

DQ(31:16)

DQ(15:0)

All 3-State

3-State

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