1

Standard Products

UT54ACS280/UT54ACTS280

9-Bit Parity Generators/Checkers

Datasheet

November 2010

www.aeroflex.com/logic

FEATURES

Generates either odd or even parity for nine data lines

Cascadable for n-bits parity

1.2μ CMOS

- Latchup immune

High speed

Low power consumption

Single 5 volt supply

Available QML Q or V processes

Flexible package

- 14-pin DIP

- 14-lead flatpack

UT54ACS280 - SMD 5962-96582

UT54ACTS280 - SMD 5962-96583

DESCRIPTION

The UT54ACS280 and the UT54ACTS280 are 9-bit parity gen-

erators/checkers that use high-performance circuitry and fea-

tures odd and even outputs to facilitate operation of either odd

or even parity application. The word-length capability is easily

expanded by cascading.

The devices are characterized over full military temperature

range of -55

°C to +125°C.

FUNCTION TABLE

LOGIC SYMBOL

PINOUTS

14-Pin DIP

Top View

14-Lead Flatpack

Top View

NUMBER OF INPUTS A THRU I

THAT ARE HIGH

OUTPUT

Σ EVEN

Σ ODD

0,2,4,6,8

H

L

1,3,5,7,9

L

H

(5)

∑

EVEN

(6)

(8)

A

Note:

1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC

Publication 617-12.

2k

(9)

B

(10)

C

(11)

D

(12)

E

(13)

F

(1)

G

(2)

H

(4)

∑

ODD

I

1

2

3

4

5

7

6

14

13

12

11

10

8

9

G

H

NC

I

∑ EVEN

∑ ODD

F

E

D

C

B

A

1

2

3

4

5

7

6

14

13

12

11

10

8

9

F

E

D

C

B

A

G

H

NC

I

∑ EVEN

∑ ODD