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UT54ACS630 Datasheet(PDF) 1 Page - Aeroflex Circuit Technology |
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UT54ACS630 Datasheet(HTML) 1 Page - Aeroflex Circuit Technology |
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1 / 10 page ![]() 1 Standard Products UT54ACS630 RadHard EDAC Datasheet May 16, 2012 www.aeroflex.com/radhard FEATURES DC operating voltage range 4.5V to 5.5V Input logic levels - VIL = 30% of VCC - VIH = 70% of VCC Fast propagation delay 11ns (max) m Commercial RadHardTM CMOS - Total dose: 100K rad(Si) - Single Event Latchup immune - SEU Onset LET: >108 MeV-cm2/mg Standard Microcircuit Drawing 5962-06239 - QML Q and V Package: - 28-lead flatpack DESCRIPTION The UT54ACS630 is a RadHard 16-bit parallel error detection and correction circuit. It uses a modified Hamming code to gen- erate a 6-bit checkword from each 16-bit data word. The check- word is stored with the data word during a memory write cycle; during a memory read cycle a 22-bit word is taken from memory and checked for errors. Single bit errors in the data words are flagged and corrected. Single bit errors in the checkword are flagged, but not corrected. The position of the incorrect bit is pinpointed, in both cases, by the 6-bit error syndrome code which is output during the error correction cycle. PIN DESCRIPTION Pin Names Description S0, S1 Mode Control Inputs DBn Bidirectional Data Bus CBn Bidirectional Checkbit Bus SEF Single Error Flag Output DEF Double Error Flag Output 1 2 3 4 5 7 6 28 27 26 25 24 22 23 DEF DB0 DB1 DB2 DB3 DB4 DB5 VDD SEF S1 S0 CB0 CB2 CB1 28-Lead Flatpack Top View 8 9 10 11 12 13 14 21 20 19 18 17 16 15 DB6 DB7 DB8 DB9 DB10 DB11 VSS CB3 CB4 CB5 DB15 DB14 DB13 DB12 |
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