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SL11RIDE
Document #: 38-08007 Rev. **
Page 25 of 27
Figure 10-1. Compact Flash Design Note
10.8
CPU Speed Control
10.8.1
Speed Control Register (0xC008: R/W)
The Speed Control Register allows the SL11R processor to operate at a number of speed selections. A four-bit divider (SPD3-0
+ 1) selects the speed as shown below. Speed will also depend on the clock multiplier. See Configuration Register (0xC006: R/W)
for more information.
D3-D0
SPD3-SPD0
Speed selection bits
Table 10-6. Power Switch Operation
Power switch operation
PWC Signal
PVCC Output
High
OFF
Low
ON
Table 10-7. Compact Flash Design
Name
Description
VCC
+5V from USB Power or external power
RPU
10-k
Ω pull-up resistor
RPURS
10-k
Ω pull-up resistor
RRS
1-k
Ω series resistor (This depends on transistor requirement)
CD_DET
Card detection uses to detect card present or not. It need 10k pull-up to +3.3VDC.
PWC_RESET
Hardware Reset to the card after power on
PWC
Power control use to turn power on/off when the card insert/remove
PVCC
Power supply to Compact Flash. It must provide enough current and voltage to the card.
D15-D4
D3
D2
D1
D0
0
SPD3
SPD2
SPD1
SPD0
12K
+
10
µF
220
MMBT2907A
VCC
0.1
µF
CFVCC
FROM SL11RIDE
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