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AD6679 Datasheet(PDF) 53 Page - Analog Devices |
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AD6679 Datasheet(HTML) 53 Page - Analog Devices |
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53 / 81 page  Data Sheet AD6679 Rev. B | Page 53 of 81 Chip Application Layer Chip Decimation Ratio DDC Input Type DDC Output Type Bandwidth Per DDC1 No. of Virtual Converters Required Register Settings2 Two DDCs 4 Complex Complex 19.25% × fS 4 Register 0x200 = 0x02 (two DDCs, I/Q selected) Register 0x201 = 0x02 (chip decimate by 4) Register 0x310, Register 0x330 = 0x80 (complex mixer, 0 dB gain, variable IF, complex outputs, HB2 + HB1 filters) Register 0x311, Register 0x331 = 0x04 (DDC I input = ADC Channel A, DDC Q input = ADC Channel B) Register 0x314, Register 0x315, Register 0x320, Register 0x321 = FTW and POW set as required by application for DDC 0 Register 0x334, Register 0x335, Register 0x340, Register 0x341 = FTW and POW set as required by application for DDC 1 Two DDCs 4 Complex Real 9.63% × fS 2 Register 0x200 = 0x22 (two DDCs, I only selected) Register 0x201 = 0x02 (chip decimate by 4) Register 0x310, Register 0x330 = 0x89 (complex mixer, 0 dB gain, variable IF, real output, HB3 + HB2 + HB1 filters) Register 0x311, Register 0x331 = 0x04 (DDC I input = ADC Channel A, DDC Q input = ADC Channel B) Register 0x314, Register 0x315, Register 0x320, Register 0x321 = FTW and POW set as required by application for DDC 0 Register 0x334, Register 0x335, Register 0x340, Register 0x341 = FTW and POW set as required by application for DDC 1 Two DDCs 4 Real Real 9.63% × fS 2 Register 0x200 = 0x22 (two DDCs, I only selected) Register 0x201 = 0x02 (chip decimate by 4) Register 0x310, Register 0x330 = 0x49 (real mixer, 6 dB gain, variable IF, real output, HB3 + HB2 + HB1 filters) Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A, DDC 0 Q input = ADC Channel A) Register 0x331 = 0x05 (DDC 1 I input = ADC Channel B, DDC 1 Q input = ADC Channel B) Register 0x314, Register 0x315, Register 0x320, Register 0x321 = FTW and POW set as required by application for DDC 0 Register 0x334, Register 0x335, Register 0x340, Register 0x341 = FTW and POW set as required by application for DDC 1 Two DDCs 4 Real Complex 19.25% × fS 4 Register 0x200 = 0x02 (two DDCs, I/Q selected) Register 0x201 = 0x02 (chip decimate by 4) Register 0x310, Register 0x330 = 0x40 (real mixer, 6 dB gain, variable IF, complex output, HB2 + HB1 filters) Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A, DDC 0 Q input = ADC Channel A) Register 0x331 = 0x05 (DDC 1 I input = ADC Channel B, DDC 1 Q input = ADC Channel B) Register 0x314, Register 0x315, Register 0x320, Register 0x321 = FTW and POW set as required by application for DDC 0 Register 0x334, Register 0x335, Register 0x340, Register 0x341 = FTW and POW set as required by application for DDC 1 |
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