CIN and COUT GND are close together

Keep path of FET’s gate short

Limit surface of switch node

to reduce capacitance

LM1771

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SNVS446D – JUNE 2006 – REVISED JANUARY 2016

10 Layout

10.1 Layout Guidelines

The LM1771, like all switching regulators, requires careful attention to layout to ensure optimal performance. The

following steps must be taken to aid in the layout. For more information refer to Application Note AN-1299

(SNVA074).

1. Ensure that the ground connections of the input capacitor, output capacitor and NMOS are as close as

possible. Ideally these must all be grounded together in close proximity on the component side of the board.

2. Keep the switch node small to minimize EMI without degrading thermal cooling of the FETs.

3. Locate the feedback resistors close to the IC and keep the feedback trace as short as possible. Do not run

any feedback traces near the switch node.

4. Keep the gate traces short and keep them away from the switch node as much as possible.

close to the chip ground, as possible.

10.2 Layout Examples

Figure 26. LM1771 Layout Example (Top)

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