8

Rev:A Date: 11/20/03

SP6681 High Efficiency Boost Charge Pump Regulator

© Copyright 2002 Sipex Corporation

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5

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1

R

5

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2

1

0

2

C2

.

2 µ

V

0

1

/

F0

3

0

.

0

Ω

R

5

X

/

5

0

8

0

0

0

1

6

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8

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7

4

8

/

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D

TK

5

7

4

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1

R

5

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6

1

2

3

C7

.

4 µ

V

0

1

/

F0

2

0

.

0

Ω

R

5

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6

0

2

1

1

1

4

9

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4

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5

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2

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6

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12

.

2 µ

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0

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R

7

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6

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8

8

8

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TG

M

5

2

2

J

B

2

1

2

K

M

L2

.

2 µ

V

0

1

/

F0

3

0

.

0

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R

5

X

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5

0

8

0

8

8

8

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5

2

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4

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TL

M

5

7

4

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6

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.

4 µ

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0

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7

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6

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2

1

The SP6681 circuit shown in figure 5 acts as a

3.3V in to 5V out for biasing the two 5V Logic

Level N-channel MOSFETs used in a step-

down DC/DC converter.

The high current

switching path is from the +3.3V bus through

the N-channel MOSFETs and inductor L1 to the

output capacitors.

To fully enhance Logic-

Level N-channel MOSFETs, +5V is needed

from the SP6681 output to the SP6120 VCC pin,

which supplies the low-side MOSFET MN1

with a 0V to 5V gate pulse through the GL pin.

Table 2. Suggested Low ESR Cermic Surface Mount Capacitors.

For the top-side MOSFET MN2 (which has a

floating gate driver biased at the BST pin), the

boost pin BST is charge pumped up from the 0

to 3.3V switching at the switch node pin SWN,

with an additional 5V from SP6681 output,

through the DBST diode to a total of 8.3V when

the SWN is at 3.3V, or a total of 5V from gate to

source to fully enhance the MOSFET MN2. For

a more detailed schematic of a step-down DC/

DC converter, see the SP6120 datasheet.

Figure 5. SP6681 Circuit as a 3.3V to 5.0V Boost for 5V N-Channel MOSFETs in Buck DC/DC Converter Circuit.

SP6120

VCC

VFB

PGND

BST

GH

SWN

GL

MN2

CIN

1.9V

1A to 7A

VOUT

RF

COUT

RI

MN1

DBST

3.3V

VIN

L1

2.2µF

2.2µF

2.2µF

SP6681

VOUT

CF1P

VIN

CD4

Cx8

CF2P

CF1N

GND

CF2N

CLK

10

9

8

7

6

1

2

3

4

5

4.7µF

130kHz Internal Clock

+5VOUT

CBST