4

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PI6C490086

RevB

2/16/2012

PI6C490086

PLL Clock Multiplier

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

Input Frequency

Fundamental Crystal

25

MHz

Input Clock

25

Output Rise Time

20% to 80% 25MHz, Note 1

1

ns

Output Fall Time

80% to 20% 25MHz, Note 1

1

Output Rise Time

20% to 80% 8.192MHz, Note 1

2

Output Fall Time

80% to 20% 8.192MHz, Note 1

2

Duty Cycle

Note 2

50

53

%

Output Frequency Synthesis Error

0

ppm

Clock Phase Jitter (RMS)

25MHz only, Note 2

0.5

1.5

ps

Additive Jitter

25MHz, Note 3

500

fs

Absolute Period Jitter (pk-pk)

8.192MHz

+/-100

ps

1. Note 1: Measured with 7 pF lump load.

2. Note 2: 12 kHz to 20 MHz offset frequency using a crystal input.

3. Note 3: CLKIN input with X2 floating.

4. Note 4: Do not drive this device without a crystal or valid clock input

VDD

CLOAD

VDD

GND GND

CLK out

OUTPUTS

0.1µF

0.1µF

CMOS Test Configuration

Crystal Oscillator Circuit

C1

20pF

Crystal�(C

C2

20pF

X1

X2

12-0165