ADC10461CIWM datasheet(12/16 Pages) NSC

12 / 16 page

Functional Description (Continued)

SIMILAR PRODUCT DIFFERENCES

The ADC1046x, ADC1046x and ADC1066x (where "x" indi-

cates the number of multiplexer inputs) are similar devices

with different specification limits. The differences in these

device families are summarized below.

Device

Family

ILE, TUE,

PSS

THD, SNR,

ENOB

Max.

Conversion

Time

ADC1046x

Guaranteed

900ns

ADC1046x

Guaranteed

900ns

ADC1066x

Guaranteed

466ns

Applications Information

1.0 MODES OF OPERATION

The ADC10461, ADC10462, and ADC10464 have two basic

digital interface modes. Figure 1 and Figure 2 are timing

diagrams for the two modes. The ADC10462 and ADC10464

have input multiplexers that are controlled by the logic levels

on pins S

0 and S1 when S/H goes low. Tables 1, 2 are truth

tables showing how the input channels are assigned.

Mode 1

In this mode, the S/H pin controls the start of conversion. S/H

is pulled low for a minimum of 250 ns. This causes the

comparators in the “coarse” flash converter to become ac-

tive. When S/H goes high, the result of the coarse conver-

sion is latched and the “fine” conversion begins. After 600 ns

(typical), INT goes low, indicating that the conversion results

are latched and can be read by pulling RD low. Note that CS

must be low to enable S/H or RD. CS is internally “ANDed”

with S/H and RD; the input voltage is sampled when CS and

S/H are low, and data is read when CS and RD are low. INT

is reset high on the rising edge of RD.

TABLE 1. Input Multiplexer Programming

ADC10464

Channel

IN0

IN1

IN2

IN3

TABLE 2. Input Multiplexer Programming

ADC10462

Channel

IN0

IN1

Mode 2

In Mode 2, also called “RD mode”, the S/H and RD pins are

tied together. A conversion is initiated by pulling both pins

low. The A/D converter samples the input voltage and

causes the coarse comparators to become active. An inter-

nal timer then terminates the coarse conversion and begins

the fine conversion. 850 ns (typical) after S/H and RD are

pull low, INT goes low, indicating that the conversion is

completed. Approximately 20 ns later the data appearing on

the TRI-STATE output pins will be valid. Note that data will

appear on these pins throughout the conversion, but until

INT goes low the data at the output pins will be the result of

the previous conversion.

2.0 REFERENCE CONSIDERATIONS

The ADC10461, ADC10462, and ADC10464 each have two

reference inputs. These inputs, V

REF+ and VREF−, are fully

differential and define the zero to full-scale range of the input

signal. The reference inputs can be connected to span the

entire supply voltage range (V

REF− =0V, VREF+ =VCC) for

ratiometric applications, or they can be connected to differ-

ent voltages (as long as they are between ground and V

CC)

when other input spans are required.

Reducing the overall V

REF span to less than 5V increases

the sensitivity of the converter (e.g., if V

REF = 2V, then 1 LSB

= 1.953 mV). Note, however, that linearity and offset errors

become larger when lower reference voltages are used. See

the Typical Performance Curves for more information. For

this reason, reference voltages less than 2V are not recom-

mended.

In most applications, V

REF− will simply be connected to

ground, but it is often useful to have an input span that is

offset from ground. This situation is easily accommodated by

the

reference

configuration

used

the ADC10461,

ADC10462, and ADC10464. V

REF− can be connected to a

voltage other than ground as long as the voltage source

connected to this pin is capable of sinking the converter’s

reference current (12.5 mA Max @ V

REF = 5V). If VREF− is

connected to a voltage other than ground, bypass it with

multiple capacitors.

Since the resistance between the two reference inputs can

be as low as 400

Ω, the voltage source driving the reference

inputs should have low output impedance. Any noise on

either reference input is a potential cause of conversion

errors, so each of these pins must be supplied with a clean,

low noise voltage source. Each reference pin should be

bypassed with a 10 µF tantalum and a 0.1 µF ceramic.

3.0 THE ANALOG INPUT

The ADC10461, ADC10462, and ADC10464 sample the

analog input voltage once every conversion cycle. When this

happens, the input is briefly connected to an impedance

approximately equal to 600

Ω in series with 35 pF. Short-

duration current spikes can be observed at the analog input

during normal operation. These spikes are normal and do

not degrade the converter’s performance.

Large source impedances can slow the charging of the

sampling capacitors and degrade conversion accuracy.

Therefore, only signal sources with output impedances less

than 500

Ω should be used if rated accuracy is to be

achieved at the minimum sample time (250 ns maximum). If

the sampling time is increased, the source impedance can

be larger. If a signal source has a high output impedance, its

output should be buffered with an operational amplifier. The

operational amplifier’s output should be well-behaved when

driving a switched 35 pF/600

Ω load. Any ringing or voltage

shifts at the op amp’s output during the sampling period can

result in conversion errors.

Correct conversion results will be obtained for input voltages

greater than GND − 50 mV and less than V

+ + 50 mV. Do not

allow the signal source to drive the analog input pin beyond

the Absolute Maximum Rating. If an analog input pin is

forced beyond these voltages, the current flowing through

the pin should be limited to 5 mA or less to avoid permanent

ADC10461CIWM Datasheet(PDF) 12 Page - National Semiconductor (TI)

ADC10461CIWM Datasheet(HTML) 12 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Datasheet Download

Link URL