PI3HDX412BD

3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis

17

www.pericom.com

03/24/14

All trademarks are property of their respective owners.

Layout and Decoupling Capacitor Placement Consideration

y

y

Each 0.1 µF decoupling capacitor should be placed as close as possible to each VDD pin.

y

y

VDD and GND planes should be used to provide a low impedance path for power and ground.

y

y

Via holes should be placed to connect to VDD and GND planes directly.

y

y

Trace should be as wide as possible

y

y

Trace should be as short as possible.

y

y

The placement of decoupling capacitor and the way of routing trace should consider the power flowing criteria.

y

y

10 µF Capacitor should also be placed closed to our part and should be placed in the middle location of 0.1 µF

capacitors.

y

y

Avoid the large current circuit placed close to our part; especially when it is shared the same VDD and GND planes.

Since large current flowing on our VDD or GND planes will generate a potential variation on the VDD or GND of our

part.

Decoupling Capacitor Placement Diagram

14-0020