ADC12062 datasheet(17/20 Pages) NSC

17 / 20 page

Applications Information (Continued)

edge) of an MM74HC4538 one-shot The 1k resistor and 12

pF capacitor set the pulse length to approximately 100 ns

The SH pulse stream for the converter appears on the Q

output of the HC4538 This is the SH clock generator used

on the ADC12062EVAL evaluation board For lower power

a CMOS inverter-based crystal oscillator can be used in

place of the DIP crystal oscillator See Application Note

AN-340 in the National Semiconductor CMOS Logic Data-

book for more information on CMOS crystal oscillators

80 COMMON APPLICATION PITFALLS

Driving inputs (analog or digital) outside power supply

rails

The Absolute Maximum Ratings state that all inputs

must be between GND b 300 mV and VCC a 300 mV This

rule is most often broken when the power supply to the

converter is turned off but other devices connected to it (op

amps microprocessors) still have power Note that if there

is no power to the converter DGND e AGND e DVCC e

AVCC e 0V so all inputs should be within g300 mV of

AGND and DGND

Driving a high capacitance digital data bus

The more

capacitance the data bus has to charge for each conver-

sion the more instantaneous digital current required from

DVCC and DGND These large current spikes can couple

back to the analog section decreasing the SNR of the con-

verter While adequate supply bypassing and separate ana-

log and digital ground planes will reduce this problem buff-

ering the digital data outputs (with a pair of MM74HC541s

for example) may be necessary if the converter must drive a

heavily loaded databus

90 APPLICATIONS

2’s Complement Output

TLH11490 – 24

Ping-Ponging between VIN1 and VIN2

TLH11490 – 25

ADC12062 Datasheet(PDF) 17 Page - National Semiconductor (TI)