MB9B100A datasheet(9/109 Pages) SPANSION

9 / 109 page

D a t a S h e e t

MB9B100A-DS706-00020-2v0-E, December 15, 2014

CONFIDENTIAL

 Clock and Reset

[Clocks]

Five clock sources (2 ext. osc, 2 CR osc, and Main PLL) that are dynamically selectable.

・Main Clock

: 4MHz to 48MHz

・Sub Clock

: 32.768kHz

・Built-in high-speed CR Clock

: 4MHz

・Built-in low-speed CR Clock

: 100kHz

・Main PLL Clock

[Resets]

・Reset requests from INITX pins

・Power-on reset

・Software reset

・Watchdog timers reset

・Low-voltage detector reset

・Clock supervisor reset

 Clock Super Visor (CSV)

Clocks generated by CR oscillators are used to supervise abnormality of the external clocks.

・External OSC clock failure (clock stop) is detected, reset is asserted.

・External OSC frequency anomaly is detected, interrupt or reset is asserted.

 Low Voltage Detector (LVD)

This series include 2-stage monitoring of voltage on the VCC. When the voltage falls below the voltage has

been set, Low Voltage Detector generates an interrupt or reset.

・LVD1: error reporting via interrupt

・LVD2: auto-reset operation

 Low-Power Consumption Mode

Three low-power consumption modes supported.

・SLEEP

・TIMER

・STOP

 Debug

・Serial Wire JTAG Debug Port (SWJ-DP)

・Embedded Trace Macrocells (ETM) provide comprehensive debug and trace facilities.

 Power Supply

・VCC

= 2.7V to 5.5V: Correspond to the wide range voltage.

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