ADC12H034 datasheet(36/41 Pages) NSC

36 / 41 page

Application Hints (Continued)

are shown in the table of Electrical Characteristics, and

spectral plots of S/(N + D) are included in the typical perfor-

mance curves.

The A/D converter’s noise and distortion levels will change

with the frequency of the input signal, with more distortion

and noise occurring at higher signal frequencies. This can be

seen in the S/(N + D) versus frequency curves.

Effective number of bits can also be useful in describing the

A/D’s noise performance. An ideal A/D converter will have

some amount of quantization noise, determined by its reso-

lution, which will yield an optimum S/N ratio given by the

following equation:

S/N = (6.02xn+ 1.76) dB

where n is the A/D’s resolution in bits.

S/(N + D) (or SINAD) is a combination of S/N (or SNR) and

distortion and is considered to be an overall measure of an

A/D converter performance. S/(N + D) is defined as:

and the effective number of Bits (ENOB) is defined as:

As an example, this device with a differential signed 5V,

1 kHz sine wave input signal will typically have a S/(N + D) of

77 dB, which is equivalent to 12.5 effective bits.

15.0 AN RS232 SERIAL INTERFACE

Shown on the following page is a schematic for an RS232

interface to any IBM and compatible PCs. The DTR, RTS,

and CTS RS232 signal lines are buffered via level transla-

tors and connected to the ADC12038’s DI, SCLK, and DO

pins, respectively. The D flip flop drives the CS control line.

01135444

Note: VA

+,V

+, and V

REF

+ on the ADC12038 each have 0.01 µF and 0.1 µF chip caps, and 10 µF tantalum caps. All logic devices are bypassed with 0.1 µF

caps.

The assignment of the RS232 port is shown below

COM1 Input Address

3FE

CTS

Output Address

3FC

RTS

DTR

A sample program, written in Microsoft QuickBasic, is shown

on the next page. The program prompts for data mode select

instruction to be sent to the A/D. This can be found from the

Mode Programming table shown earlier. The data should be

entered in “1”s and “0”s as shown in the table with DI0 first.

Next the program prompts for the number of SCLKs required

for the programmed mode select instruction. For instance, to

send all “0”s to the A/D, selects CH0 as the +input, CH1 as

the −input, 12-bit conversion, and 13-bit MSB first data

output format (if the sign bit was not turned off by a previous

instruction). This would require 13 SCLK periods since the

output data format is 13 bits. The part powers up with No

Auto Cal, No Auto Zero, 10 CCLK Acquisition Time, 12-bit

conversion, data out with sign, power up, 12- or 13-bit MSB

first, and user mode. Auto Cal, Auto Zero, Power Up and

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