ADC14071 datasheet(13/18 Pages) NSC

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Applications Information (Continued)

For single ended operation, one of the analog inputs should

be connected to a voltage equal to the reference voltage,

with the common mode voltage of the driven input equal to

that same voltage. The peak-to-peak input signal should be

twice the reference voltage to minimize SNR and SINAD

loss. For example, set the V

REF to 1.0V, bias VIN− to 1.0V

and drive V

IN+ with signal range of 0V to 2.0V.

The V

IN+ and the VIN− inputs of the ADC14071 consist of an

analog switch followed by a switched-capacitor amplifier.

The capacitance seen at the analog input pins changes with

the clock level, appearing as 14 pF when the clock is low,

and 5 pF when the clock is high. Since a dynamic capaci-

tance is more difficult to drive than is a fixed capacitance,

choose the driving amplifier carefully. The LM6172 is a good

amplifier for driving the ADC14071.

The internal switching action at the analog inputs causes en-

ergy to be output from the input pins. As the driving source

tries to compensate for this, it adds noise to the signal. To

prevent this, use 33

Ω series resistors at each of the signal

inputs with a 0.0022 µF capacitor across the inputs, as can

be seen in

Figures 6, 7. These components should be

placed close to the ADC as the input pins of the ADC is the

most sensitive part of the system and this is the last oppor-

tunity to filter the input.

2.0 DIGITAL INPUTS

Digital inputs consist of CLOCK, OE and PD.

2.1 CLOCK

The CLOCK signal controls the timing of the sampling pro-

cess. Drive the clock input with a stable, low phase jitter

clock signal in the range of 25 kHz to 8 MHz and rise and fall

times of less than 4 ns. The trace carrying the clock signal

should be as short as possible. This trace should not cross

any other signal line, analog or digital, not even at 90˚.

The CLOCK signal also drives the internal state machine. If

the clock is interrupted, the charge on internal capacitors can

dissipate to the point where the output data will lose accu-

racy.

The CLOCK pin should be terminated with a series 100

Ω re-

sistor and 200 pF capacitor to ground located within two cen-

timeters of the ADC14071 clock pin, as shown in

Figure 5.

Whenever the trace between the clock source and the ADC

clock pin is greater than 2 cm, use a 50

Ω series resistor in

the clock line, located within 2 cm of the driving source.

2.2 OE

The OE pin, when low, puts the output pins into a high im-

pedance state. Be very careful when driving a high capaci-

tance bus. The more capacitance the output drivers must

charge for each conversion, the more instantaneous digital

current flows through DR V

D and DR GND. These large

charging current spikes can couple into the analog circuitry,

degrading dynamic performance. Adequate bypassing and

maintaining separate analog and digital ground planes will

reduce this problem.

Additionally, bus capacitance beyond the specified 20 pF/pin

will cause t

OD to increase, making it difficult to properly latch

the ADC output data. The result could, again, be an apparent

reduction in dynamic performance.

The digital data outputs should be buffered (with 74ACQ541,

for example). Dynamic performance can also be improved

by adding series resistors at each digital output, close to the

ADC14071, which reduces the energy coupled back into the

converter output pins by limiting the output current. A reason-

able value for these resistors is 47

Ω.

2.3 PD

The PD pin, when high, holds the ADC14071 in a

power-down mode to conserve power when the converter is

not being used. In this state the power consumption is 20

mW. The output data pins may change randomly when the

PD pin is high. Power consumption during power-down is not

affected by the clock frequency, or by whether there is a

clock signal present. The data in the pipeline is corrupted

while in the power down mode.

3.0 OUTPUTS

The ADC14071 has 15 digital outputs: 14 Data Output pins

and OR (Out of Range).

The output pins are TTL/CMOS compatible and the output

data format is straight binary. Valid data is present at these

outputs while the OE pin is low. While the t

OD time provides

information about output timing, a simple way to capture a

valid output is to latch the data on the

falling edge of the con-

version clock (pin 11).

To minimize noise due to output switching, minimize the load

currents at the digital outputs. This can be done by connect-

ing buffers between the ADC outputs and any other circuitry.

Only one input should be connected to each output pin. Ad-

ditionally, inserting series resistors of 47

Ω to 56Ω at the digi-

tal outputs, close to the ADC pins, will isolate the outputs

from trace and other circuitry capacitances and limit the out-

put currents which could otherwise result in performance

degradation, as discussed in Section 2.2. See

Figure 5.

The OR pin indicates when the input signal is under- or

over-range. This pin and the MSB, used together, will indi-

cate whether the input is out of range low or high.

DS101101-31

FIGURE 4. Angular Errors between the Two Input

Signals Will Reduce the Output Level

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