ADC16061CCVT datasheet(11/20 Pages) NSC

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Specification Definitions

APERTURE JITTER is the variation in aperture delay from

sample to sample. Aperture jitter shows up as input noise.

APERTURE DELAY is the time required after the falling

edge of the clock for the sampling switch to open. In other

words, for the Track/Hold circuit to go from ’track’ mode into

the ’hold’ mode. The Track/Hold circuit affectively stops cap-

turing the input signal and goes into the ’hold’ mode t

AD after

the fall of the clock.

OFFSET ERROR is the difference between the ideal LSB

transition to the actual transition point. The LSB transition

should occur when V

IN+=VIN−.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE

BITS) is another method of specifying Signal-to-Noise and

Distortion Ratio, or SINAD. ENOB is defined as (SINAD

−1.76) / 6.02.

FULL SCALE ERROR is the difference between the input

voltage [(V

IN+)−(VIN−)] just causing a transition to positive

full scale and V

REF − 1.5 LSB, where VREF is(VREF+ IN)−

REF−IN).

FULL POWER BANDWIDTH is a measure of the frequency

at which the reconstructed output fundamental drops 3 dB

below its low frequency value for a full scale input. The test

is performed with f

IN equal to 100 kHz plus integral multiples

of f

CLK. The input frequency at which the output is −3 dB

relative to the low frequency input signal is the full power

bandwidth.

INTERMODULATION DISTORTION (IMD) is the creation of

additional spectral components as a result of two sinusoidal

frequencies being applied to the ADC input at the same time.

It is defined as the ratio of the power in the intermodulation

products to the total power in the original frequencies. IMD is

usually expressed in dB.

INTEGRAL NON-LINEARITY (INL) is a measure of the de-

viation of each individual code from a line drawn from nega-

tive full scale (1⁄2 LSB below the first code transition) through

positive full scale (the last code transition). The deviation of

any given code from this straight line is measured from the

center of that code value.

PIPELINE DELAY (LATENCY) is the number of clock cycles

between initiation of conversion and when that data is pre-

sented to the output stage. Data for any given sample is

available the Pipeline Delay plus the Output Delay after that

sample is taken. New data is available at every clock cycle,

but the data lags the conversion by the pipeline delay.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in

dB, of the rms value of the input signal to the rms value of the

sum of all other spectral components below one-half the

sampling frequency, not including harmonics or dc.

SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SI-

NAD)) is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral com-

ponents below half the clock frequency, including harmonics

but excluding dc.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-

ence, expressed in dB, between the rms values of the input

signal and the peak spurious signal, where a spurious signal

is any signal present in the output spectrum that is not

present at the input.

TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-

pressed in dB or dBc, of the rms total of the first six harmonic

components, to the rms value of the input signal.

Timing Diagrams

DS100889-15

TIMING DIAGRAM 1. Output Timing

ADC16061CCVT Datasheet(PDF) 11 Page - National Semiconductor (TI)

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