MSP430F149 datasheet(27/59 Pages) TI

27 / 59 page

MSP430x13x, MSP430x14x, MSP430x14x1

MIXED SIGNAL MICROCONTROLLER

SLAS272F − JULY 2000 − REVISED JUNE 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

outputs − Ports P1, P2, P3, P4, P5, and P6

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IOH(max) = −1 mA,

VCC = 2.2 V,

See Note 1

VCC−0.25

VCC

VOH

High-level output voltage

IOH(max) = −6 mA,

VCC = 2.2 V,

See Note 2

VCC−0.6

VCC

VOH

High-level output voltage

IOH(max) = −1 mA,

VCC = 3 V,

See Note 1

VCC−0.25

VCC

IOH(max) = −6 mA,

VCC = 3 V,

See Note 2

VCC−0.6

VCC

IOL(max) = 1.5 mA,

VCC = 2.2 V,

See Note 1

VSS

VSS+0.25

VOL

Low-level output voltage

IOL(max) = 6 mA,

VCC = 2.2 V,

See Note 2

VSS

VSS+0.6

VOL

Low-level output voltage

IOL(max) = 1.5 mA,

VCC = 3 V,

See Note 1

VSS

VSS+0.25

IOL(max) = 6 mA,

VCC = 3 V,

See Note 2

VSS

VSS+0.6

NOTES:

1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±6 mA to satisfy the maximum

specified voltage drop.

2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±24 mA to satisfy the maximum

specified voltage drop.

output frequency

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fTAx

TA0..2, TB0−TB6,

Internal clock source, SMCLK signal

applied (see Note 1)

CL = 20 pF

fSystem

MHz

fACLK,

fMCLK,

fSMCLK

P5.6/ACLK, P5.4/MCLK, P5.5/SMCLK

CL = 20 pF

fSystem

MHz

P2.0/ACLK

fACLK = fLFXT1 = fXT1

40%

60%

P2.0/ACLK

CL = 20 pF,

= 2.2 V / 3 V

fACLK = fLFXT1 = fLF

30%

70%

CL = 20 pF,

VCC = 2.2 V / 3 V fACLK = fLFXT1/n

50%

fSMCLK = fLFXT1 = fXT1

40%

60%

tXdc

Duty cycle of output frequency,

P1.4/SMCLK,

fSMCLK = fLFXT1 = fLF

35%

65%

Xdc

P1.4/SMCLK,

CL = 20 pF,

VCC = 2.2 V / 3 V

fSMCLK = fLFXT1/n

50%−

15 ns

50%

50%−

15 ns

VCC = 2.2 V / 3 V

fSMCLK = fDCOCLK

50%−

15 ns

50%

50%−

15 ns

NOTE 1: The limits of the system clock MCLK has to be met; the system (MCLK) frequency should not exceed the limits. MCLK and SMCLK

frequencies can be different.

MSP430F149 Datasheet(PDF) 27 Page - Texas Instruments

MSP430F149 Datasheet(HTML) 27 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL