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GTL2006PW Datasheet(PDF) 4 Page - NXP Semiconductors |
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GTL2006PW Datasheet(HTML) 4 Page - NXP Semiconductors |
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4 / 14 page ![]() Philips Semiconductors Product data GTL2006 13-bit GTL–/GTL/GTL+ to LVTTL translator 2004 Jun 21 4 LOGIC SYMBOL SW01092 GTL VREF 2BI 1BI 10AI1 10AI2 GTL INPUT 11BI 11BO 10BO2 10BO1 4AO 3AO 2AO 1AO LVTTL I/O GTL OUTPUTS GTL INPUTS 5BI LVTTL I/O 11A (OPEN DRAIN) 5A (OPEN DRAIN) 6A (OPEN DRAIN) LVTTL INPUTS 7BO1 1 2 3 4 5 6 26 25 24 22 21 20 19 18 17 16 15 8 9 10 11 12 13 GTL2006 27 LVTTL INPUT 8AI GTL INPUT 9BI LVTTL OUTPUTS 7BO2 6BI 8BO 23 3BI 4BI 9AO LVTTL OUTPUT 7 GTL OUTPUTS GTL INPUTS LVTTL OUTPUTS DELAY1 DELAY1 NOTE: 1. The enable on 7BO1/7BO2 include a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a low glitch on the 7BO1/7BO2 outputs. Figure 2. Logic symbol |
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