TMS27C256 32768 BY 8-BIT UV ERASABLE

TMS27PC256 32768 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997

4

POST OFFICE BOX 1443

initializing ( TMS27PC256 )

The one-time programmable TMS27PC256 PROM is provided with all bits in the logic high state, then logic lows

are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.

SNAP! Pulse programming

The 256K EPROM and OTP PROM are programmed using the TI SNAP! Pulse programming algorithm

illustrated by the flowchart in Figure 1, which programs in a nominal time of four seconds. Actual programming

time varies as a function of the programmer used.

Data is presented in parallel (eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, E is pulsed.

The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (

µs) followed by a byte

verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-

µs

pulses per byte are provided before a failure is recognized.

can be programmed when the devices are connected in parallel. Locations can be programmed in any order.

program inhibit

Programming can be inhibited by maintaining a high level input on the E pin.

program verify

signature mode

The signature mode provides access to a binary code identifying the manufacturer and type. This mode is

activated when A9 is forced to 12 V. Two identifier bytes are accessed by toggling A0. All other addresses must

be held low. The signature code for these devices is 9704. A0 selects the manufacturer’s code 97 (Hex), and

A0 high selects the device code 04, as shown in Table 3.

Table 3. Signature Mode

IDENTIFIER†

PINS

IDENTIFIER†

A0

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

HEX

MANUFACTURER CODE

VIL

1

0

0

1

0

1

1

1

97

DEVICE CODE

VIH

0

0

0

0

0

1

0

0

04

† E = G = VIL, A9 = VH, A1–A8 = VIL, A10–A15 = VIL, VPP = VCC, PGM = VIH or VIL.