DIR1703

SLES007– JULY 2001

9

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system clock output (continued)

Table 5. System Clock Operation Mode

CONDITIONS

CLOCK AND DATA OUTPUTS

MODE

CKSEL

S/PDIF

DATA

SCKO

BCKO

LRCKO

DOUT

BRATE

UNLOCK

CS. UR

BIT

AD.

EMFLG

After

RESET

Default PLL†

(128, 256, 384, 512

fS)

Default

PLL†

(64 fS)

Default

PLL†

(1 fS)

MUTE

LOW

HIGH

LOW

LOW

PLL

LOW

YES

PLL

(128, 256, 384, 512

fS)

PLL

(64 fS)

PLL

(1 fS)

DATA

DETECT

LOW

DATA

DATA

NO

HOLD‡

(128, 256, 384, 512

fS)

HOLD‡

(64 fS)

HOLD‡

(1 fS)

MUTE

HOLD‡

HIGH

Unknown

HOLD‡

After

RESET

Crystal

(128, 256, 384, 512

fS)

Crystal

(64 fS)

Crystal

(1 fS)

MUTE

LOW

HIGH

LOW

LOW

CRYSTAL

HIGH

YES

Crystal

(128, 256, 384, 512

fS)

Crystal

(64 fS)

Crystal

(1 fS)

MUTE

DETECT

LOW

Unknown

LOW

NO

Crystal

(128, 256, 384, 512

fS)

Crystal

(64 fS)

Crystal

(1 fS)

MUTE

Unknown

HIGH

Unknown

LOW

† In the PLL mode, the DIR1703 will be the same frequencies as the crystal mode after RESET; however, the frequency error is below 1%.

‡ Holds the latest tracked frequency.

SCKO timing

L

H

0.8 V

2 V

System Clock Pulse

Cycle Time†

tSCKH

tSCKL

SCKO

SCKO Clock Pulse Width High

tSCKH

7 ns (min)

SCKO Clock Pulse Width Low

tSCKL

7 ns (min)

† 1/128 fS, 1/256 fS, 1/384 fS or 1/512 fS.