6

ICS93735

0579E—08/06/03

Recommended Operation Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Analog / Core Supply Voltag

2.3

2.5

2.7

V

Input Voltage Level

22.5

3

V

Output Differential Pair

Crossing Voltage

1.32

V

1.23

1.25

Timing Requirements

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Operating Clock Frequency

1

Input Voltage level: 0-2.50V

22

340

MHz

Input Clock Duty Cycle

1

40

50

60

%

Clock Stabilization

1

from VDD = 2.5V to 1% target frequency

100

µs

1. Guaranteed by design, not 100% tested in production.

Switching Characteristics

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

66 MHz

465263

100 / 125 / 133 MHz

27

33

40

Phase Error

1

100MHz, input clock 0-2.5V, 0.8ns rise/fall

-113

ps

Output to output Skew

1

input clock 0-2.5V, 0.8ns rise/fall

66

98

ps

Low-to-high level Propagation

CLK_IN to any output,

Delay Time, Bypass Mode

1

100MHz, Load = 120 W / 12 pF

Pulse Skew

1

ps

Duty Cycle (Sign Ended)

1,3

DC

no loads, 66 MHz to 167MHz

50.2

51.3

%

Rise Time

1

Single-ended 20-80 %; Load=120W/12pF

400

490

622

ps

Fall Time

1

Single-ended 20-80 %; Load=120W/12pF

435

579

711

ps

1. Guaranteed by design, not 100% tested in production.

2. Refers to transistion on non-inverting period.

3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies.

Cycle to cycle Jitter

1,2

ps

3.67

3.68

ns