TMS320VC5416-160 datasheet(9/98 Pages) TI

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TMS320VC5416 Features

TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095O – MARCH 1999 – REVISED JANUARY 2005

• Arithmetic Instructions With Parallel Store and

• Advanced Multibus Architecture With Three

Parallel Load

Separate 16-Bit Data Memory Buses and One

Program Memory Bus

• Conditional Store Instructions

• 40-Bit Arithmetic Logic Unit (ALU) Including a

• Fast Return From Interrupt

40-Bit Barrel Shifter and Two Independent

• On-Chip Peripherals

40-Bit Accumulators

–

Software-Programmable Wait-State

• 17- × 17-Bit Parallel Multiplier Coupled to a

Generator and Programmable

40-Bit Dedicated Adder for Non-Pipelined

Bank-Switching

Single-Cycle Multiply/Accumulate (MAC)

–

On-Chip Programmable Phase-Locked

Operation

Loop (PLL) Clock Generator With External

Clock Source

• Compare, Select, and Store Unit (CSSU) for the

–

One 16-Bit Timer

Add/Compare Selection of the Viterbi Operator

–

Six-Channel Direct Memory Access (DMA)

• Exponent Encoder to Compute an Exponent

Controller

Value of a 40-Bit Accumulator Value in a

–

Three Multichannel Buffered Serial Ports

Single Cycle

(McBSPs)

• Two Address Generators With Eight Auxiliary

–

8/16-Bit Enhanced Parallel Host-Port

Registers and Two Auxiliary Register

Interface (HPI8/16)

Arithmetic Units (ARAUs)

• Power Consumption Control With IDLE1,

• Data Bus With a Bus Holder Feature

IDLE2, and IDLE3 Instructions With

• Extended Addressing Mode for 8M × 16-Bit

Power-Down Modes

Maximum Addressable External Program

• CLKOUT Off Control to Disable CLKOUT

Space

• On-Chip Scan-Based Emulation Logic, IEEE

• 128K x 16-Bit On-Chip RAM Composed of:

Std 1149.1 (JTAG) Boundary Scan Logic(1)

–

Eight Blocks of 8K

× 16-Bit On-Chip

• 144-Pin Ball Grid Array (BGA)(GGU Suffix)

Dual-Access Program/Data RAM

• 144-Pin Low-Profile Quad Flatpack

–

Eight Blocks of 8K

× 16-Bit On-Chip

(LQFP)(PGE Suffix)

Single-Access Program RAM

• 6.25-ns Single-Cycle Fixed-Point Instruction

• 16K × 16-Bit On-Chip ROM Configured for

Execution Time (160 MIPS)

Program Memory

• 8.33-ns Single-Cycle Fixed-Point Instruction

• Enhanced External Parallel Interface (XIO2)

Execution Time (120 MIPS)

• Single-Instruction-Repeat and Block-Repeat

• 3.3-V I/O Supply Voltage (160 and 120 MIPS)

Operations for Program Code

• 1.6-V Core Supply Voltage (160 MIPS)

• Block-Memory-Move Instructions for Better

Program and Data Management

• 1.5-V Core Supply Voltage (120 MIPS)

• Instructions With a 32-Bit Long Word Operand

• Instructions With Two- or Three-Operand

(1)

IEEE Standard 1149.1-1990 Standard-Test-Access Port and

Reads

Boundary Scan Architecture

TMS320C54x, TMS320 are trademarks of Texas Instruments.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TMS320VC5416-160 Datasheet(PDF) 9 Page - Texas Instruments

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