DAC1006LCWM datasheet(19/22 Pages) NSC

19 / 22 page

NOTE DATA HOLD TIME REDUCED TO THAT OF DM74LS374 (

10 ns)

FIGURE 20 Isolating Data Bus from DAC Circuitry to Eliminate Digital Noise Coupling

TLH5688 – 26

FIGURE 21 Digitally Controlled AmplifierAttenuator

74 Digitally Controlled AmplifierAttenuator

An unusual application of the DAC

Figure 21 applies the

input voltage via the on-chip feedback resistor The lower

op amp automatically adjusts the VREF IN voltage such that

IOUT1 is equal to the input current (VIN RfB) The magnitude

of this VREF IN voltage depends on the digital word which is

in the DAC register IOUT2 then depends upon both the

magnitude of VIN and the digital word The second op amp

converts IOUT2 to a voltage VOUT which is given by

VOUTeVIN

1023bN

J where 0kNs1023

Note that Ne0 (or a digital code of all zeros) is not allowed

or this will cause the output amplifier to saturate at either

VMAX depending on the sign of VIN

To provide a digitally controlled divider the output op amp

can be eliminated Ground the IOUT2 pin of the DAC and

VOUT is now taken from the lower op amp (which also drives

the VREF input of the DAC) The expression for VOUT is now

given by

VOUTeb

VIN

where MeDigital input (expressed as a

fractional binary number)

0kMk1

DAC1006LCWM Datasheet(PDF) 19 Page - National Semiconductor (TI)