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CY7C960
CY7C961
2
REGION/
AMTABLE
CY7C964 CONTROLLER
POWER-ON
RESET
GENERATOR
AM[5:0]
SYSRESET*
AS*
DS0*
DS1*
DTACK*
WRITE*
BR*
BBSY*
BERR*
BGIN*
BGOUT*
CLK
REGION [3:0]
IRQ*
IACK*
IACKIN*
IACKOUT*
DATA BYTE
ENABLE
CONTROLLER
DATABYTE
LANE
DECODER
LOCAL
CONTROL
CIRCUIT
DRAM
CONTROLLER
REFRESH
CONTROLLER
TIMING
GENERATOR
VME
CONTROL
INTERFACE
VME
INTERRUPT
INTERFACE
CS [5:0]
DBE [3:0]
LACK*
LBERR*
LDEN*
PREN*
SWDEN*
R/W
LA [7:1]
LWORD
LOCAL
ADDRESS
CONTROLLER
CHIP SELECT
OUTPUT
PATTERN TABLE
LD [7:0]
DMA CHANNEL
REGISTERS
DMA
CONTROLLER
LOCK
CONTROLLER
Top View
TQFP
c960–2
64 63
61
62
60
2
3
1
32
33
34
12
13
15
14
16
4
5
31
30
59 58
17
9
10
8
7
6
11
18 19
21
20
22 23
26
25
2728 29
24
40
39
37
38
36
35
41
42
43
48
46
47
45
44
53 52
50
51
49
57 56
LA7
LA6
LA5
LA4
IRQ*
LA3
LA1
AM5
VCC
DS1*
LWORD
LAEN
LA2
LACK*
LIRQ*
LDEN*
CS0
CS1
AM3
GND
REGION1
REGION0
DENIN*
REGION2
54
55
GND
LDS
DENIN1*
VCC
WRITE*
REGION3/CS2
AM4
CY7C960 Pin Configuration
CY7C961 Logic Block Diagram
c960–3
CLK
SELECTLM
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