DS2740USLASHT datasheet(13/15 Pages) DALLAS

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DS2740

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READ-TIME SLOTS

A read-time slot is initiated when the bus master pulls the 1-Wire bus line from a logic-high level to a

logic-low level. The bus master must keep the bus line low for at least 1ms and then release it to allow the

DS2740 to present valid data. The bus master can then sample the data tRDV from the start of the read-

time slot. By the end of the read-time slot, the DS2740 releases the bus line and allows it to be pulled

high by the external pullup resistor. All read-time slots must be tSLOT in duration with a 1ms minimum

recovery time, tREC, between cycles. See Figure 12 for more information.

Figure 12. 1-WIRE WRITE- AND READ-TIME SLOTS

LINE TYPE LEGEND:

Bus master active low

DS2740 active low

Resistor pullup

Both bus master and

DS2740 active low

tSLOT

VPULLUP

GND

READ 0 SLOT

READ 1 SLOT

tSLOT

tREC

tRDV

Master Sample Window

tRDV

VPULLUP

GND

tSLOT

Standard

tLOW1

tSLOT

WRITE 0 SLOT

WRITE 1 SLOT

tLOW0

tREC

DS2740 Sample Window

MIN

TYP

MAX

DS2740 Sample Window

MIN

TYP

MAX

Overdrive

Mode

DS2740U/T Datasheet(PDF) 13 Page - Dallas Semiconductor

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