DAC5686IPZP datasheet(25/53 Pages) TI1

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align

CLK2

0.5 ns

CLK2

CLK1

DA[15:0]

DB[15:0]

∆ < talign

T0002−01

DAC5686

www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009

In PLL CLOCK MODE, the DAC is driven at the input sample rate (unless the data is multiplexed) through

CLK1/CLK1C. CLK2/CLK2C is not used. In this case, there is no phase ambiguity on the clock. The DAC

generates the higher-speed DAC sample-rate clock using an internal PLL/VCO. In PLL clock mode, the user

provides a differential external reference clock on CLK1/CLK1C.

A type-4 phase-frequency detector (PFD) in the internal PLL compares this reference clock to a feedback

clock and drives the PLL to maintain synchronization between the two clocks. The feedback clock is

generated by dividing the VCO output by 1×, 2×, 4×, or 8× as selected by the prescaler (div[1:0]). The

output of the prescaler is the DAC sample rate clock and is divided down to generate clocks at ÷2, ÷4, ÷8,

and ÷16. The feedback clock is selected by the registers sel[1:0], and then is fed back to the PFD for

synchronization to the input clock. Because the feedback clock is also used for the data input rate, the

interpolation rate of the DAC5686 is the ratio of DAC output clock to the feedback clock. The PLLLOCK pin

is an output that indicates when the PLL has achieved lock. An external RC low-pass PLL filter is provided

by the user at pin LPF. See the low-pass filter section for filter-setting calculations. This is the only mode

where the LPF filter applies.

Use of the internal PLL/VCO generally results in higher phase noise than if an externally generated DAC

clock is used. At low frequencies, such as baseband signals, use of the internal PLL/VCO likely has a

minimal effect on signal quality. For higher IF frequencies, such as in single sideband or quadrature

modulation mode, the PLL/VCO phase noise can result in degradation of the signal. Note that most of the

DAC5686 plots and typical specifications are in external clock mode (PLLVDD = 0). Use of the DAC5686

PLL/VCO also can result in higher out-of-band spurious signals (see the Non-Harmonic Clock-Related

Spurious Signals section).

3. PLLVDD = 0 V and dual_clk = 1: DUAL CLOCK MODE

In DUAL CLOCK MODE, the DAC is driven at the DAC sample rate through CLK2/CLK2C and at the input

data rate through CLK1/CLK1C. The DUAL CLOCK MODE has the advantage of a clean external clock for

DAC sampling without the phase ambiguity. The edges of CLK1 and CLK2 must be aligned to within talign

(See Figure 26), defined as

where fCLK2 is the clock frequency of CLK2. For example, talign = 0.5 ns at fCLK2 = 500 MHz and 1.5 ns at fCLK2

= 250 MHz.

Figure 26. DAC and Data Clock Mode

The CDC7005 from Texas Instruments is recommended for providing phase-aligned clocks at different

frequencies for this application.

Table 3 provides a summary of the clock configurations with corresponding data rate ranges.

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