DLP4710FQL datasheet(17/39 Pages) TI1

17 / 39 page

Datum 'E' area (1 place)

Thermal Interface Area

Datum 'A' area (3 places)

Clamping and Electrical Interface Area

DLP4710

www.ti.com

DLPS056B – NOVEMBER 2014 – REVISED JULY 2016

Product Folder Links: DLP4710

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(1)

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

6.8 Switching Characteristics

(1)

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPD

Output propagation, Clock to Q, rising

edge of LS_CLK input to LS_RDATA

output. Figure 12

CL = 5 pF

11.1

CL = 10 pF

11.3

CL = 85 pF

Slew rate, LS_RDATA

0.5

V/ns

Output duty cycle distortion, LS_RDATA

40%

60%

6.9 System Mounting Interface Loads

PARAMETER

MIN

NOM

MAX

UNIT

Maximum system mounting interface

load to be applied to the:

Thermal Interface Area (see Figure 14)

Clamping and Electrical Interface Area (see Figure 14)

110

Figure 14. System Interface Loads

DLP4710FQL Datasheet(PDF) 17 Page - Texas Instruments

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