CDC208

DUAL 1LINE TO 4LINE CLOCK DRIVER

WITH 3STATE OUTPUTS

SCAS109F − APRIL 1990 − REVISED OCTOBER 1998

6

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT FOR OUTPUTS

S1

2

× VCC

Open

GND

500

Ω

500

Ω

TEST

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

S1

Open

2

× VCC

GND

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2

× VCC

(see Note C)

Output

Waveform 2

S1 at 2

× VCC

(see Note C)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

≈ VCC

0 V

50% VCC

0 V

3 V

(see Note A)

50% VCC

20% VCC

80% VCC

tPLH

tPHL

1.5 V

1.5 V

3 V

0 V

50% VCC

50% VCC

VOH

VOL

Input

(see Note B)

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR

≤ 10 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.

For testing pulse duration: tr = tf = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

Figure 1. Load Circuit and Voltage Waveforms