REV. 0

AD1981A

–16–

AC ’97 2.2 AMAP-Compliant Default SPDIF Slot Assignments

CODEC ID

Function

SPSA = 00

SPSA = 01

SPSA = 10

SPSA = 11

00

2-Ch Primary w/SPDIF

3 and 4

7 and 8 [default]

6 and 9

10 and 11

00

4-Ch Primary w/SPDIF

3 and 4

7 and 8

6 and 9 [default]

10 and 11

00

6-Ch Primary w/SPDIF

3 and 4

7 and 8

6 and 9

10 and 11 [default]

01

+2-Ch Secondary w/SPDIF

3 and 4

7 and 8

6 and 9 [default]

01

+4-Ch Secondary w/SPDIF

3 and 4

7 and 8

6 and 9

10 and 11 [default]

10

+2-Ch Secondary w/SPDIF

3 and 4

7 and 8

6 and 9 [default]

10

+4-Ch Secondary w/SPDIF

3 and 4

7 and 8

6 and 9

10 and 11 [default]

11

+2-Ch Secondary w/SPDIF

3 and 4

7 and 8

6 and 9

10 and 11 [default]

PCM Front DAC Rate Register (Index 2Ch)

*This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz.

SR[15:0]

Sample Rate: The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. If “0”

is written to VRA, then the sample rate is reset to 48k.

PCM ADC Rate Register (Index 32h)

Reg Num Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0 Default

32h

PCM L/R ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h

This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz.

SR[15:0]

Sample Rate: The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments.

If “0” is written to VRA, then the sample rate is reset to 48k.

SPDIF Control Register (Index 3Ah)

Reg. Num. Name

D15 D14

D13

D12

D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

3Ah

SPDIF Control

V

X SPSR1 SPSR0

L

CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY /AUD PRO 2000h

*Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case).

With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF bit in Register 2Ah is “0”). This

ensures that control and status information start up correctly at the beginning of SPDIF transmission.

PRO

Professional: “1” indicates professional use of channel status, “0” indicates consumer.

/AUD

Non-Audio: “1” indicates data is non-PCM format, “0” data is PCM.

COPY

Copyright: “1” indicates copyright is asserted, “0” copyright is not asserted.

PRE

Pre-Emphasis: “1” indicates filter pre-emphasis is 50/15 msec, “0” pre-emphasis is none.

CC[6:0]

Category Code: Programmed according to IEC standards, or as appropriate.

L

Generation Level: Programmed according to IEC standards, or as appropriate.

SPSR[1:0]

SPDIF Transmit Sample Rate:

SPSR[1:0] = “00” Transmit Sample Rate = 44.1 kHz

SPSR[1:0] = “01” Reserved

SPSR[1:0] = “10” Transmit Sample Rate = 48 kHz (Reset Default)

SPSR[1:0] = “11” Not Supported

V

Validity: This bit affects the “Validity” flag (Bit 28 transmitted in each SPDIF L/R subframe) and enables the

SPDIF transmitter to maintain connection during error or mute conditions.

V = 1 Each SPDIF subframe (L + R) has Bit 28 set to “1.” This tags both samples as invalid.

V = 0 Each SPDIF subframe (L + R) has Bit 28 set to “0” for valid data and “1” for invalid data (error condition).

Note that when V = 0, asserting the VFORCE bit (D15) in Register 2Ah (Ext’d Audio Stat/Ctrl) will force the

“Validity” flag low, marking both samples as valid.

Reg Num Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0 Default

2Ch

PCM Front DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h