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Table XVI. External Memory Map

A[2:0] Name

Comment

111

Access Control

Auto Increment

Broadcast

5–2: Instruction[3:0]

1–0: A[9:8]

110

Channel Address

7–0: A[7:0]

101

SOFT_SYNC Control

PN_EN

Test_MUX_Select

Hop

Start

SYNC 3

SYNC 2

SYNC 1

SYNC 0

100

PIN_SYNC Control

Toggle IEN for BIST

First SYNC Only

Hop_En

Start_En

SYNC_EN A

SYNC_EN B

SYNC_EN C

SYNC_EN D

011

SLEEP (Write Only)

7–6: Reserved (low)

Access Input/Output Port

Control Registers

Reserved low

SLEEP 3

SLEEP 2

SLEEP 1

SLEEP 0

010

Data Register 2 (DR2)

7–4: Reserved

3–0: D[19:16]

001

Data Register 1 (DR1)

15–8: D[15:8]

000

Data Register 0 (DR0)

7–0: D[7:0]

Access Control Register (ACR)

The access control register serves to define the channel or

channels that receive an access from the microport or serial

port control.

Bit 7 of this register is the Auto-Increment bit. If this bit is 1,

the CAR register described below will increment its value after

every read/write access to the channel. It essentially means that

CAR (external address 6) need not be written for every memory

access, and the user can write to DR2, DR1, DR0 continuously

while accessing consecutive memory location in each access.

This allows blocks of address space such as coefficient memory

to be initialized more efficiently.

Bit 6 of the register is the Broadcast bit and determines how

Bits 5–2 are interpreted. If Broadcast is 0, then Bits 4–2, which

are referred to as Instruction bits (Instruction[2:0]), are com-

pared with the CHIPn_ID[2:0] pins (n = 0 when /CS0 is used,

and n = 1 when /CS1 is used). The instruction that matches the

CHIPn_ID[2:0] pins will determine the access. This allows up

to two chips to be connected to the same port and their

memory to be mapped without external logic. This also allows

the same serial port of a host processor to configure up to eight

chips. If the Broadcast bit is high, the Instruction[3:0] word

allows multiple AD6635 channels and/or chips to be configured

simultaneously, independent of the CHIPn_ID[2:0] pins. There

are seven possible instructions that are defined in the table

below. This is useful for smart antenna systems in which mul-

tiple channels listening to a single antenna or carrier can be

configured simultaneously. An x in the table represents “don’t

care” in the digital decoding.

Table XVII. Microport Instructions

Instruction

Comment

0000

All Chips and All Channels Get Access

0001

Channel 0,1,2 of All Chips Get Access

0010

Channel 1,2,3 of All Chips Get Access

0100

All Chips Get Access

1000

All Chips with CHIPn_ID[2:0] = xxx Get

Access

* (same as previous instruction)

1100

All Chips with CHIPn_ID[2:0] = xx0 Get

Access

1110

All Chips with CHIPn_ID[2:0] = xx1 Get

Access

*A[9:8] bits control which channel is decoded for the access.

Note that CHIP0_ID[2:0] is used when

CS0 is used for

programming. CHIP1_ID[2:0] is used when

CS1 is used

for programming.

When broadcast is enabled (Bit 6 set high), the readback is not

valid because of the potential for internal bus contention. There-

fore, if readback is subsequently desired, the broadcast bit should

be set low.

Bits 1–0 of this register are address bits that decode which of

the four channels are being accessed, i.e., Channels 0–3 when

CS0 is used, and similarly, Channels 4–7 when CS1 is used. If

the Instruction bits decode an access to multiple channels, these

bits are ignored. If the Instruction decodes an access to a subset

of chips, the A[9:8] bits will otherwise determine the channel

being accessed. It should be noted that if access to input/output

control registers (Bit 5 of external address 3) is set, then A[9:8]

are not decoded.

Channel Address Register (CAR)

This register represents the 8-bit internal address of each chan-

nel. If the Auto-Increment bit of the ACR is 1, this value will be

incremented after every access to the DR0 register, which will

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