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TIMING REQUIREMENTS

SWITCHING CHARACTERISTICS

CDCVF857

SCAS047F – MARCH 2003 – REVISED MAY 2007

ELECTRICAL CHARACTERISTICS (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Part-to-part input

∆C

1

pF

capacitance variation

Input capacitance difference

between CLK and CLK,

0.25

pF

FBIN, and FBIN

over recommended ranges of supply voltage and operating free-air temperature

PARAMETER

MIN

MAX

UNIT

Operating clock frequency

60

220

MHz

Application clock frequency

90

220

Input clock duty cycle

40%

60%

10

µs

30

ns

(1)

The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be

the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This

parameter does not apply for input modulation under SSC application.

(2)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Low-to-high level propagation delay time

Test mode/CLK to any output

3.5

ns

High-to-low level propagation delay time

Test mode/CLK to any output

3.5

ns

100 MHz (PC1600)

–65

65

Jitter (period), see Figure 7

ps

133/167/200 MHz (PC2100/2700/3200)

–30

30

100 MHz (PC1600)

–50

50

Jitter (cycle-to-cycle), see Figure 4

ps

133/167/200 MHz (PC2100/2700/3200)

–35

35

100 MHz (PC1600)

–100

100

Half-period jitter, see Figure 8

ps

133/167/200 MHz (PC2100/2700/3200)

–75

75

Output clock slew rate, see Figure 9

Load: 120

Ω, 14 pF

1

2

V/ns

Static phase offset, see Figure 5

100/133/167/200 MHz

–50

50

ps

Output skew, see Figure 6

Load: 120

Ω, 14 pF; 100/133/167/200 MHz

40

ps

(1)

Refers to the transition of the noninverting output.

(2)

This parameter is assured by design but cannot be 100% production tested.

7

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