DP83901AV datasheet(56/62 Pages) NSC

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150 Switching Characteristics AC Specs DP83901A Note All Timing is Preliminary (Continued)

Wait State Insertion

TLF10469 – 40

Symbol

Parameter

Min

Max

Units

ews

External Wait Setup to T3 0Clock (Note 1)

ewr

External Wait Release Time (Note 1)

Note 1

The addition of wait states affects the count of deserialized bytes and is limited to a number of bus clock cycles depending on the bus clock and network

rates The allowable wait states are found in the table below (Assumes 10 Mbitsec data rate)

BSCK (MHz)

Max

of Wait States

Byte Transfer

Word Transfer

Table assumes 10 MHz network clock

The number of allowable wait states in byte mode can be

calculated using

W(byte mode) e

8tnw

45 tbsck

Number of Wait States

tnw

Network Clock Period

tbsck

BSCK Period

The number of allowable wait states in word mode can be

calculated using

W(word mode) e

5tnw

2 tbsck

DP83901AV Datasheet(PDF) 56 Page - National Semiconductor (TI)

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