AD9860 datasheet(22/32 Pages) AD

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AD9860/AD9862

RECEIVE SECTION COMPONENTS

The receive block is configurable to process input signals of dif-

ferent formats and has special features such as an input buffer,

gain stage, and decimation filters. The AD9860/AD9862 receive

path block diagram is shown in Figure 6. The block diagram can

be broken into the following stages: Input Buffer (Block A),

RxPGA (Block B), dual, 10-/12-bit, 64 MSPS ADC (Block C),

Decimation filter (Block D), Digital Hilbert Block (Block E),

and a Data Output Multiplexer. The function of each stage is

explained in the following paragraphs.

Input Buffer Stage

The input buffer stage buffers the input signal on-chip for both

receive paths. The buffer stage has two main benefits, providing

a constant input impedance and reducing any “kick-back” noise

that might be generated on-chip, affecting the analog input signal.

The Rx path sampling mode can be split into two categories,

depending on the frequency of the input signal. When sampling

input signals up to Nyquist of the ADC, the sampling is referred to

as Nyquist sampling. When sampling at rates above ADC Nyquist

rate, the sampling is referred to as IF sampling or undersampling.

For Nyquist sampling, the input buffer provides a constant 200

impedance over the entire input signal range. The constant input

impedance accommodates matching networks to ensure proper

transfer of signal to the input of the device. The input buffer is

self-biased to ~ 2 V, and therefore the input signal should be

ac-coupled to the Rx differential input or have a common-mode

voltage of about 2 V. If an external buffer is present, the internal

input buffer can be bypassed and powered down to reduce power

consumption. The input buffer accepts up to a 2 V p-p input

signal for maximum SNR performance. Optimal THD perfor-

mance occurs with 1 V p-p input signal.

For IF sampling, the input buffer can be used with input signals

up to about 100 MHz, the 3 dB bandwidth of the buffer. When

undersampling the input signal, the output spectrum will contain

an aliased version of the original, higher frequency signal. As was

the case with Nyquist sampling, the input signal should be

ac-coupled to the Rx differential input or have a common-mode

voltage of ~ 2 V. For input signals over 100 MHz to about 250 MHz,

the input buffer needs to be bypassed and an external input

buffer is required. In the case that the input buffer is bypassed,

the input circuit is a switched capacitor network. The switching

input impedance during the sample phase is about 1/(2( )FC),

where F is the input frequency and C is the input capacitance

(about 4 pF). During hold mode, the input impedance is > 1 M

RxPGA

The RxPGA stage has a Programmable Gain Amplifier that can be

used to amplify the input signal to utilize the entire input range

of the ADC. The RxPGA stage provides a 0 dB to 20 dB gain

range in steps of about 1 dB. The Rx channel independent gain

control is accomplished through two 5-bit SPI programmable

RxPGA A/B registers. The gain curve is linear in dB with a minimum

gain setting (0 dB, nominally) of hex00 and a maximum gain

setting (20 dB, nominally) of hex14.

The RxPGA stage can provide up to a 2 V p-p signal to the

ADC input.

Analog-to-Digital (A/D) Converter

The analog-to-digital converter (ADC) stage consists of two

high performance 10-/12-bit, 64 MSPS analog-to-digital (A/D)

converters. The dual A/D converter paths are fully independent,

except for a shared internal bandgap reference source, VREF. Each

of the A/D converter’s paths consists of a front-end sample and

hold amplifier followed by a pipelined, switched capacitor, A/D

converter. The pipelined A/D converter is divided into three sections,

consisting of a 4-bit first stage followed by eight 1.5-bit stages and

a final 3-bit flash. Each stage provides sufficient overlap to correct

for flash errors in the preceding stages. The quantized outputs

from each stage are combined into a final 12-bit result through

a digital correction logic block. The pipelined architecture permits

the first stage to operate on a new input sample while the remain-

ing stages operate on preceding samples. Sampling occurs on the

rising clock edge.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash A/D connected to a switched capacitor DAC and

interstage residue amplifier (MDAC). The residue amplifier magni-

fies the difference between the reconstructed DAC output and the

flash input for the next stage in the pipeline. One bit of redundancy

is used in each one of the stages to facilitate digital correction of

flash errors. The last stage simply consists of a flash A/D.

A stable and accurate 1.0 V bandgap voltage reference is built into

the AD9860/AD9862 and is used to set a 2 V p-p differential input

range. The internally generated reference should be decoupled

at the VREF pin using a 10

mF and a 0.1 mF capacitor in parallel

to ground. Separate top and bottom references, VRT and VRB,

for each converter are generated from VREF and should also be

decoupled. Recommended decoupling for the top and bottom

references consists of using 10

mF and 0.1 mF capacitors in parallel

between the differential reference pins, and a 0.1

mF capacitor

ADC

LOW-PASS

DECIMATION

FILTER

PGA

VIN+A

VIN–A

ADC

PGA

VIN+B

VIN–B

HILBERT

FILTER

BLOCK A BLOCK B

BLOCK C

BLOCK D

BLOCK E

RxA DATA

[0:11]

RxB DATA

[0:11]

Figure 6. Receive Section Block Diagram

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