AD9864-EB datasheet(28/44 Pages) AD

28 / 44 page

AD9864

–10

–20

–30

–50

–40

NORMALIZED FREQUENCY (RELATIVE TO

fOUT)

–60

–70

–80

0.5

1.0

1.5

2.0

NOTCH AT ALL ALIAS FREQUENCIES

When tuning the LC tank, the sampling clock frequency must

be stable and the LNA/mixer, LO synthesizer, and ADC must

all be placed in standby. Large LO and IF signals present at the

inputs of the AD9864 can corrupt the calibration. These signals

should be minimized or disabled during the calibration

sequence. Tuning is triggered when the ADC is taken out of

standby if the TUNE_LC bit of Register 0x1C has been set. This

bit will clear when the tuning operation is complete (less than

6 ms). The tuning codes can be read from the 3-bit CAPL1

(0x1D) and the 6-bit CAPL0 (0x1E) registers.

In a similar manner, tuning of the RC resonator is activated if

the TUNE_RC bit of Register 0x1C is set when the ADC is

taken out of standby. This bit will clear when tuning is com-

plete. The tuning code can be read from the CAPR (0x1F)

the LC tank and the active RC resonator in succession. During

tuning, the ADC is not operational and neither data nor a clock

is available from the SSI port. Table 15 lists the recommended

sequence of the SPI commands for tuning the ADC, and

Table 16 lists all of the SPI registers associated with band-pass

Σ-∆ ADC.

Figure 48. Signal Transfer Function of the Band-Pass Σ-∆

Modulator from 0 fCLK to 2fCLK

Figure 49 shows the nominal signal transfer function magni-

tude for frequencies near the fCLK/8 pass band. The width of the

pass band determines the transfer function droop, but even at

the lowest oversampling ratio (48) where the pass band edges

are at ±fCLK/192 (±0.005 fCLK), the gain variation is less than

0.5 dB. Note that the amount of attenuation offered by the sig-

nal transfer function near fCLK/8 should also be considered when

determining the narrow-band IF filtering requirements preced-

ing the AD9864.

Table 15. Tuning Sequence

Address (Hex)

Value

Comments

0x00

0x45

LO synthesizer, LNA/mixer, and

ADC are placed in standby.*

0x1C

0x03

Set TUNE_LC and TUNE_RC. Wait

for CLK to stabilize if CLK

synthesizer used.

0x00

0x44

Take the ADC out of standby. Wait

for 0x1C to clear (<6 ms).

LNA/mixer can now be taken out

of standby

*If external CLK VCO or source used, the CLK oscillator must also be disabled.

Large IF or LO signals can corrupt the calibration; these signals should be

disabled during the calibration sequence.

–0.10

–5

–10

NORMALIZED FREQUENCY (RELATIVE TO

fCLK)

–15

–20

–0.05

0.05

0.10

Table 16. SPI Registers Associated with Band-Pass Σ-∆ ADC

Address

(Hex)

Value

Width

Default

Value

Name

0x00

(7:0)

0xFF

STBY

0x1C

(1)

(0)

TUNE_LC

TUNE_RC

0x1D

(2:0)

CAPL1 (2:0)

0x1E

(5:0)

0x00

CAPL1 (5:0)

0x1F

(7:0)

0x00

CAPR

Figure 49. Magnitude of the ADC’s Signal Transfer Function near fCLK/8

Tuning of the Σ-∆ modulator’s two continuous-time resonators

is essential in realizing the ADC’s full dynamic range and must

be performed upon system startup. To facilitate tuning of the

LC tank, a capacitor array is internally connected to the MXOP

and MXON pins. The capacitance of this array is programmable

from 0 pF to 200 pF ± 20% and can be programmed either

automatically or manually via the SPI port. The capacitors of

the active RC resonator are similarly programmable. Note that

the AD9864 can be placed in and out of its standby mode with-

out retuning since the tuning codes are stored in the SPI Registers.

Once the AD9864 has been tuned, the noise figure degradation

attributed solely to the temperature drift of the LC and RC

resonators is minimal. Since the drift of the RC resonator is

actually negligible compared to that of the LC resonator, the

external L and C components’ temperature drift characteristics

tend to dominate. Figure 50 shows the degradation in noise

figure as the product of the LC value is allowed to vary from

–12.5% to +12.5%. Note that the noise figure remains relatively

Rev. 0 | Page 28 of 44

AD9864-EB Datasheet(PDF) 28 Page - Analog Devices

AD9864-EB Datasheet(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL