DI

DE0

DE1

DE2

DE3

B0

A0

B1

A1

B2

A2

B3

A3

DE0

DE1

DE2

VDD

B0

A0

A1

B1

1

2

3

4

16

14

13

15

GND

DI

N/C

DE3

5

6

7

8

B2

A2

A3

B3

12

10

9

11

DS91M124

SNLS287E – AUGUST 2008 – REVISED APRIL 2013

www.ti.com

Pin Diagram

Figure 1. SOIC Package

See Package Number D0016A

Logic Diagram

Pin Descriptions

Number

Name

I/O, Type

Description

1, 2, 3, 8

DE

I, LVCMOS

Driver enable pin: When a DE pin is low, the corresponding driver output is

disabled. When a DE pin is high, the corresponding driver output is enabled.

There is a 300 k

Ω pulldown resistor on each DE pin.

6

DI

I, LVCMOS

Driver input pin.

5

GND

Power

Ground pin.

10, 11, 14, 15

A

O, M-LVDS

Non-inverting driver output pins.

9, 12, 13, 16

B

O, M-LVDS

Inverting driver output pins.

4

Power

Power supply pin, +3.3V ± 0.3V

7

N/C

N/A

NO CONNECT pin.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

2

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