DP8390DV datasheet(37/56 Pages) NSC

37 / 56 page

130 Bus Arbitration and Timing (Continued)

SLAVE MODE TIMING

When CS is low the NIC becomes a bus slave The CPU

can then read or write any internal registers All register

access is byte wide The timing for register access is shown

below The host CPU accesses internal registers with four

address

lines

RA0 – RA3

SRD

and

SWR

strobes

ADS0 is used to latch the address when interfacing to a

multiplexed address data bus Since the NIC may be a local

bus master when the host CPU attempts to read or write to

the controller an ACK line is used to hold off the CPU until

the NIC leaves master mode Some number of BSCK cycles

is also required to allow the NIC to synchronize to the read

or write cycle

Write to Register

TLF8582 – 74

Read from Register

TLF8582 – 75

TIME BETWEEN CHIP SELECTS

The NIC requires that successive chip selects be no closer

than 4 bus clocks (BSCK) together below If the condition is

violated the NIC may glitchACK CPUs that operate from

pipelined instructions (ie

386) or have a cache (ie

486) can execute consecutive IO cycles very quickly The

solution is to delay the execution of consecutive IO cycles

by either breaking the pipeline or forcing the CPU to access

outisde it’s cache

Time between Chip Selects

TLF8582 – A1

DP8390DV Datasheet(PDF) 37 Page - National Semiconductor (TI)