ADS7890

SLAS409 − DECEMBER 2003

www.ti.com

8

LSB

MSB

th2

tsu3

tw5

td3

td2

t(cyc)

twH

twL

th4

td5

th3

tw2

t(conv)

td4

t(acq), SAMPLE

Power Up

SCLK

CS

SDO

BUSY

12

3

8

9

14

15

16

Figure 1. Device Operation With SPI Interface (FS Held High)

DEVICE OPERATION WITH DSP INTERFACE (See Figure 2)

Device operation is controlled with CS, SCLK, and FS. The frame starts with the rising edge of FS with CS

already low. The MSB is latched out first on the SDO pin. The clock cycle, with the first falling edge after the

falling edge of FS is counted as first clock. Subsequent data bits are latched out on the SDO pin with every rising

edge of further clocks (until the 14th rising edge of SCLK). The device has a built-in NAP mode. The device

enters the NAP state with an end of conversion and continues to be in this state until the 8th SCLK rising edge.

The sampling switch is closed on the 9th rising edge and the device samples the analog input [+IN− (−IN)] and

enters the conversion phase on the 16th SCLK falling edge.

CS can be pulled high at any time after this. The BUSY signal goes high to indicate the conversion is in progress

and continues to be high until the end of conversion. A new frame can be started with the end of conversion.

LSB

MSB

td2

t(cyc)

th4

th3

t(conv)

td5

t(acq), SAMPLE

Power Up

SCLK

CS

FS

SDO

BUSY

th1

tsu2

twH

twL

tsu1

tw1

td1

td4

tw2

12

3

8

9

14

15

16

Figure 2. Device Operation With DSP Interface

POWERDOWN/RESET

A low level on the PWD/RST pin puts the device in the powerdown phase. This is an asynchronous signal. As

conversions after powerup (see Figure 3) or the end of reset (see Figure 4). The device is initialized during the

first four conversions.