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ADT7461

ADT7461–SPECIFICATIONS

Table 1. ADT7461 Specifications at TA = −40°C to +120°C , VDD = 3 V to 5.5 V, unless otherwise noted.

Parameter

Min

Typ

Max

Unit

Test Conditions

POWER SUPPLY

Supply Voltage, VDD

3.0

3.30

5.5

Average Operating Supply Current, IDD

170

215

µA

0.0625 Conversions/Sec Rate1

5.5

µA

Standby Mode , –40°C ≤ TA ≤ +85°C

5.5

µA

Standby Mode, +85°C ≤ TA ≤ +120°C

Undervoltage Lockout Threshold

2.2

2.55

2.8

VDD Input, Disables ADC, Rising Edge

Power-On-Reset Threshold

2.5

TEMPERATURE-TO-DIGITAL CONVERTER

Local Sensor Accuracy

±1

±3

°C

−40°C ≤ TA ≤ +100°C, 3 V ≤ VDD ≤ 3.6 V

Resolution

°C

Remote Diode Sensor Accuracy

±1

°C

+60°C ≤ TA ≤ +100°C, −55°C ≤ TD 2 ≤ +150°C, 3 V ≤ VDD ≤ 3.6 V

±3

°C

−40°C ≤ TA ≤ +120°C, −55°C ≤ TD 2 ≤ +150°C, 3 V ≤ VDD ≤ 5.5 V

Resolution

0.25

°C

Remote Sensor Source Current

µA

High Level3

µA

Middle Level3

µA

Low Level3

Conversion Time

32.13

114.6

From Stop Bit to Conversion Complete (Both Channels) One-

Shot Mode with Averaging Switched On

3.2

12.56

One-Shot Mode with Averaging Off (i.e., Conversion Rate = 16,

32, or 64 Conversions per Second)

Maximum Series Resistance Cancelled

kΩ

Resistance Split Evenly on Both the D+ and D– Inputs

OPEN-DRAIN DIGITAL OUTPUTS

(THERM, ALERT/THERM2)

Output Low Voltage, VOL

0.4

IOUT = −6.0 mA3

High Level Output Leakage Current, IOH

0.1

µA

VOUT = VDD 3

ALERT Output Low Sink Current

ALERT forced to 0.4 V

SMBus INTERFACE3, 4

Logic Input High Voltage, VIH

2.1

3 V ≤ VDD ≤ 3.6 V

SCLK, SDATA

Logic Input Low Voltage, VIL

0.8

3 V ≤ VDD ≤ 3.6 V

SCLK, SDATA

Hysteresis

500

SMBus Output Low Sink Current

SDATA Forced to 0.6 V

Logic Input Current, IIH, IIL

−1

µA

SMBus Input Capacitance, SCLK, SDATA

SMBus Clock Frequency

400

kHz

SMBus Timeout5

User Programmable.

SCLK Falling Edge to SDATA Valid Time

µs

Master Clocking in Data

1 See Table 8 for information on other conversion rates.

2 Guaranteed by characterization but not production tested.

3 Guaranteed by design but not production tested.

4 See SMBus Timing Specifications section for more information.

5 Disabled by default. Details on how to enable it are in the SMBus section of this data sheet.

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