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ADS8364Y/2K Datasheet(PDF) 16 Page - Texas Instruments |
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ADS8364Y/2K Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 22 page  ADS8364 16 SBAS219B www.ti.com The HOLD signals will start conversion automatically on the next clock cycle. The format of the two words that can be writing to ADS8364 are shown in Table V. GETTING DATA Flexible output modes: (A0, A1, A2) The ADS8364 has three different output modes that are se- lected with A2, A1, and A0. With (A2 A1 A0) = 000 to 101, a particular channel can directly be addressed (see Table II and Figure 9). The channel address should be set at least 10ns (see Figure 9, tD9) before the falling edge of RD and should not change as long as RD is LOW. In this standard address mode, ADD will be ignored, but should be connected to either ground or supply. With (A2 A1 A0) = 110, the interface is running in a cycle mode (see Figure 11). Here, data 7 down to 0 of channel A0 is read on the first RD-signal and 15 down to 8 on the second as BYTE is HIGH. Then A1 on the second, followed by B0, B1, C0, and finally, C1 before reading A0 again. Data from channel A0 is brought to the output first after a reset-signal or after powering the part up. The third mode is a FIFO mode that is addressed with (A2 A1 A0 = 111). Data of the channel that is converted first will be read first. So, if a particular channel pair is most interesting and is converted more frequently (e.g., to get a history of a particular channel pair) then there are three output registers per channel available to store data. ADD = 1 BYTE = 0 BYTE = 1 A2A1A0 1st RD 2nd RD 1st RD 2nd RD 3rd RD 000 db15...db0 no 2nd RD db7...db0 db15...db8 no 3rd RD 001 db15...db0 no 2nd RD db7...db0 db15...db8 no 3rd RD 010 db15...db0 no 2nd RD db7...db0 db15...db8 no 3rd RD 011 db15...db0 no 2nd RD db7...db0 db15...db8 no 3rd RD 100 db15...db0 no 2nd RD db7...db0 db15...db8 no 3rd RD 101 db15...db0 no 2nd RD db7...db0 db15...db8 no 3rd RD 110 1000 0000 0000 dv a2 a1 a0 db15...db0 dv a2 a1 a0 db3 db2 db0 db7...db0 db15...db8 111 1000 0000 0000 dv a2 a1 a0 db15...db0 dv a2 a1 a0 db3 db2 db0 db7...db0 db15...db8 TABLE IV. Overview Over the Output formats Depending on the Mode in Case ADD = 1 DB7 (MSB) DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB) 1X X X ADD A2 A1 A0 0 X X X RESET HOLDA HOLDB HOLDC TABLE V. Data Register Bits. ADD = 0 BYTE = 0 BYTE = 1 A2 A1 A0 1st RD 2nd RD 1st RD 2nd RD 3rd RD 000 db15...db0 no 2nd RD db7...db0 db15...db8 no 3rd RD 001 db15...db0 no 2nd RD db7...db0 db15...db8 no 3rd RD 010 db15...db0 no 2nd RD db7...db0 db15...db8 no 3rd RD 011 db15...db0 no 2nd RD db7...db0 db15...db8 no 3rd RD 100 db15...db0 no 2nd RD db7...db0 db15...db8 no 3rd RD 101 db15...db0 no 2nd RD db7...db0 db15...db8 no 3rd RD 110 db15...db0 no 2nd RD db7...db0 db15...db8 no 3rd RD 111 db15...db0 no 2nd RD db7...db0 db15...db8 no 3rd RD TABLE III. Overview of the Output Formats Depending on the Mode (Case ADD = 0). If all the output registers are filled up with unread data and new data from an additional conversion has to get latched in, then the oldest data gets thrown away. If a read process is going on (RD-signal LOW) and new data has to be stored, then the ADS8364 will wait until the read process is finished (RD-signal going HIGH) before the new data gets latched into its output register. Again, with the ADD signal, it can be chosen if the address should be added to the output data. New data is always written into the next available register. At t0 (see Figure 12), the reset deletes all the existing data. At t1, the new data of the channels A0 and A1 are put into registers 0 and 1. At t2, the read process of channel A0 data is finished. Therefore, this data is dumped and A1 data is shifted to register 0. At t3, new data is available, this time from channels B0, B1, C0 and C1. This data is written into the next available registers (registers 1, 2, 3, and 4). On t4, the new read process of channel A1 data is finished. The new data of channel C0 and C1 at t5 is put on top (registers 4 and 5). In Cycle mode and in FIFO mode, the ADS8364 offers the ability to add the address of the channel to the output data. As there is just a 16-bit bus available (or 8-bit bus in the case byte is HIGH), an additional (RD-signal is necessary to get the information (see Table III and Table IV). The Output Code (DB15…DB0)–In the standard address mode (A2 A1 A0 = 000…101), the ADS8364 has a 16-bit output word on pins DB15…DB0 if BYTE = 0. If BYTE = 1 then two RD-impulses are necessary to first read the lower bits then the higher bits on either DB7…DB0 or DB15...DB8. The address of the channel (a2a1a0) and a data valid (dv) bit is added to the data if the ADS8364 is operated in the cycle or in the FIFO-mode and ADD is set HIGH. If BYTE = 0, then the data valid and the address of the channel is active during the first (RD-impulse (1000 0000 0000 dv a2 a1 a0). During the second (RD, the 16-bit data word can be read (db15…db0). If BYTE = 1, then three (RD-impulses are needed. On the first one, data valid, the three address bits and the data bits db3…db0 (dv, a2, a1, a0, db3, db2, db1, db0) are read, followed by the eight lower bits of the 16-bit data word |
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