CLVC16T245MDGGREP datasheet(2/17 Pages) TI1

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To Seven Other Channels

1DIR

1A1

1B1

1OE

To Seven Other Channels

2DIR

2A1

2B1

2OE

SN74LVC16T245-EP

SCES843A – JANUARY 2013 – REVISED FEBRUARY 2013

www.ti.com

DESCRIPTION (CONTINUED)

The SN74LVC16T245 is designed for asynchronous communication between two data buses. The logic levels of

the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port

outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to

the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are

activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level

applied to prevent excess ICC and ICCZ.

The SN74LVC16T245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance

state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Table 1. ORDERING INFORMATION(1)

ORDERABLE PART

PACKAGE

TOP-SIDE MARKING

VID NUMBER

NUMBER

Reel of 2000

CLVC16T245MDGGREP

V62/12667-01XE

–55°C to 125°C

TSSOP-DGG

LVC16T245M

Tube of 40

CLVC16T245MDGGEP

V62/12667-01XE-T

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

FUNCTION TABLE(1)

(EACH 8-BIT SECTION)

CONTROL INPUTS

OUTPUT CIRCUITS

OPERATION

DIR

A PORT

B PORT

Enabled

Hi-Z

B data to A bus

Hi-Z

Enabled

A data to B bus

Hi-Z

Isolation

(1)

Input circuits of the data I/Os always are active.

LOGIC DIAGRAM (POSITIVE LOGIC)

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