ADV7301A datasheet(13/68 Pages) AD

13 / 68 page

REV. A

ADV7300A/ADV7301A

–13–

Pin No.

Mnemonic

Input/Output

Function

14–18, 26–30

C0–C9

10-Bit Progressive Scan/HDTV Input Port for CrCb color data in 4:2:2 Input

Mode. In 4:4:4 Input Mode, this input port is used for the Cb (Blue/U) data.

The LSBs are set up on Pins C0 and C1. In Default Mode, the input on this

port is output on DAC E.

2CI

This input pin must be tied high (VDD_IO) for the ADV7300A/ADV7301A to

interface over the I

2C port.

ALSB

I/O

TTL Address Input. This signal sets up the LSB of the MPU address. When

this pin is tied low, the I

2C filter is activated, which reduces noise on the I2C interface.

SDA

I/O

MPU Port Serial Data Input/Output

SCLK

MPU Port Serial Interface Clock Input

P_HSYNC

IVideo Horizontal Sync Control Signal for HD Sync in Simultaneous SD/HD

Mode and HD Only Mode

P_VSYNC

IVideo Vertical Sync Control Signal for HD Sync in Simultaneous SD/HD

Mode and HD Only Mode

P_BLANK

Video Blanking Control Signal for HD Sync in Simultaneous SD/HD Mode

and HD Only Mode

RTC_SCR_TR

Multifunctional Input: Realtime Control (RTC) Input, Timing Reset Input,

and Subcarrier Reset Input

CLKIN_A

Pixel Clock Input for HD Only or SD Only Modes

RESET

IThis input resets the on-chip timing generator and sets the ADV7300A/

ADV7301A into default register setting. Reset is an active low signal.

EXT_LF

External Loop Filter for the internal PLL

35, 47

RSET2, 1

IA 760

Ω resistor must be connected from this pin to AGND and is used to

control the amplitudes of the DAC outputs.

36, 45

COMP2, 1

Compensation Pin for DACs. Connect 0.1

µF capacitor from COMP pin to V

AA.

DAC F

In SD Only Mode: Chroma/Red/V Analog Output, in HD Only Mode and

Simultaneous HD/SD: Pb/Blue (HD) Analog Output

DAC E

In SD Only Mode: Luma/Blue/U Analog Output, in HD Only Mode and

Simultaneous HD/SD: Pr/Red (HD) Analog Output

DAC D

In SD Only Mode: CVBS/Green/Y Analog Output, in HD Only Mode and

Simultaneous HD/SD: Y/Green (HD) Analog Output

AGND

Analog Ground

VAA

PAnalog Power Supply

DAC C

Chroma/Red/V SD Analog Output

DAC B

Luma/Blue/U SD Analog Output

DAC A

CVBS/Green/Y SD Analog Output

VREF

I/O

Optional External Voltage Reference Input for DACs or Voltage Reference

Output (1.235 V)

S_BLANK

I/O

Video Blanking Control Signal for SD

S_VSYNC

I/O

Video Vertical Control Signal for SD. Option to output SD VSYNC or SD

HSYNC in SD Slave Mode 0 and/or any HD Mode.

S_HSYNC

I/O

Video Horizontal Control Signal for SD. Option to output SD HSYNC or

HD HSYNC in SD Slave Mode 0 and/or any HD Mode.

51–55, 58–62

S0–S9

10-Bit Standard Definition Input Port or Progressive Scan/HDTV Input Port

for Cr (Red/V) color data in 4:4:4 Input Mode. The LSBs are set up on Pins

S0 and S1. In Default Mode, the input on this port is output on DAC F.

CLKIN_B

Pixel Clock Input. Requires a 27 MHz reference clock for Progressive Scan

Mode or a 74.25 MHz (74.1758 MHz) reference clock in HDTV Mode. This

clock input pin is only used in Simultaneous SD/HD Mode.

GND_IO

Digital Ground

ADV7301A Datasheet(PDF) 13 Page - Analog Devices

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