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DS2411P/T Datasheet(PDF) 3 Page - Dallas Semiconductor

Part # DS2411P/T
Description  Silicon Serial Number with VCC Input
PDF  11 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS2411P/T Datasheet(HTML) 3 Page - Dallas Semiconductor

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DS2411
3 of 11
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX UNITS
I/O PIN, 1-Wire RESET, PRESENCE DETECT CYCLE
Standard speed
480
640
Reset Low Time
tRSTL
Overdrive speed
60
80
µs
Standard speed
15
60
Overdrive VCC ≥ 2.2V
2
6
Presence-Detect High Time
tPDH
Overdrive VCC ≥ 1.5V
2
8.5
µs
Standard speed
60
240
Overdrive VCC ≥ 2.2V
8
24
Presence-Detect Low Time
tPDL
Overdrive VCC ≥ 1.5V
8
30
µs
Standard speed (Note 10, 3)
0.4
8
Presence-Detect Fall Time
tFPD
Overdrive speed (Note 10, 3)
0.05
1
µs
Standard speed (Note 1)
60
75
Overdrive VCC ≥ 2.2V (Note 1)
6
10
Presence-Detect Sample
Time
tMSP
Overdrive VCC ≥ 1.5V (Note 1)
8.5
10
µs
I/O PIN, 1-Wire WRITE
Standard speed (Notes 1, 13)
60
120
Overdrive VCC ≥ 2.2V (Notes 1,
13)
616
Write-0 Low Time
tW0L
Overdrive VCC ≥ 1.5V (Notes 1,
13)
816
µs
Standard speed (Notes 1, 11, 13)
5
15 -
e
Write-1 Low Time
tW1L
Overdrive speed (Notes 1, 11, 13)
1
2 -
e
µs
I/O PIN, 1-Wire READ
Standard speed (Notes 1, 11)
5
15 -
e
Read Low Time
tRL
Overdrive speed (Notes 1, 11)
1
2 -
e
µs
Standard speed (Notes 1, 12)
tRL +
d
15
Read Sample Time
tMSR
Overdrive speed (Notes 1, 12)
tRL +
d
2
µs
Note 1:
System requirement.
Note 2:
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the
system and 1-Wire recovery times. The specified value here applies to systems with only
one device and with the minimum 1-Wire recovery times. For more heavily loaded
systems, an active pullup such as that found in the DS2480B may be required. Minimum
allowable pullup resistance is slightly greater than the value necessary to produce the
absolute maximum current (20mA) during 1-Wire low times at VPUP = 5.25V assuming
VOL = 0V.
Note 3:
Not production tested.
Note 4:
VTL and VTH are functions of VCC and temperature.
Note 5:
Voltage below which during a falling edge on I/O, a logic ‘0’ is detected.
Note 6:
Voltage above which during a rising edge on I/O, a logic ‘1’ is detected.
Note 7:
After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by VHY to
be detected as logic ‘0’.
Note 8:
The I-V characteristic is linear for voltages less than 1V.
Note 9:
The earliest recognition of a negative edge is possible at tREH after VTH has been reached
on the previous edge.
Note 10:
Interval during the negative edge on I/O at the beginning of a presence-detect pulse
between the time at which the voltage is 90% of VPUP and the time at which the voltage is
10% of VPUP.



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