PCM1748ESLASH2K datasheet(31/38 Pages) TI1

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REVISION HISTORY

PCM1748

SBAS165B – MAY 2001 – REVISED APRIL 2005

DATE

REV

PAGE

SECTION

DESCRIPTION

Apr 2005

–

Global

Changed to new format

Absolute Maximum Ratings

Changed values for power supply voltage, digital input voltage, lead

temperature, and package temperature. Added supply voltage

difference, VCC – VDD < 3 V.

Package/Ordering Information

Table removed from page 2, reformatted, and appended at end of

data sheet.

Recommended Operating Con-

New table added to data sheet.

ditions

Electrical Characteristics

Storage temperature removed from Temperature Range section of

Electrical Characteristics (duplicate information in Absolute Maxi-

mum Ratings).

Pin Assignments and Terminal

Moved from page 2

Functions

Typical Performance Curves

In Figure 12, changed Y-axis label from SNR to Dynamic Range.

Power-On-Reset Functions

Added description about 1024-system-clock delay time shown in the

Figure 20 timing diagram.

Audio Serial Interface

Changed description of I2S format and condition for synchronization

from one SCK clock to three BCK clocks.

13, 14

Audio Data Formats and Timing

In Figure 21, Audio Data Input Formats, removed 32-fS availability

from left-justified format. In Figure 22, Audio Interface Timing,

corrected specification for BCK pulse cycle time.

For Table 3, Mode Control Register Map, added note to explain the

RSV table entry.

17, 18

For ATx[7:0] – Digital Attenuation Level Setting and MUTx – Soft

Mute Control, added description about incrementing/decrementing

attenuation level by one step for every 8/fS period.

For FMT[2:0] – Audio Interface Data Format, corrected default

setting from 000, 24-bit standard format, right-justified data to 101,

left-justified format, 16-to 24-bit.

Zero Flags

Added description for L-channel/R-channel common zero flag.

Connection Diagram

In Figure 28, corrected capacitor polarity for VDD decoupling

capacitor.

26, 27

PCB Layout Guidelines

In Figure 30 and Figure 31, deleted extraneous signal lines. In

Figure 31, changed leftmost block to Digital Logic and Audio

Processor.

Dynamic Range

Corrected parameters in test setup diagram, Figure 36.

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