PRE

V

GND

J

K

Q

Q

Regulated 3.3 V

CC

µC or

µC

System Logic

LEDs

System Logic

CLK

CLR

SN74LVC112A

SCAS289M – JANUARY 1993 – REVISED DECEMBER 2014

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10 Application and Implementation

10.1 Application Information

SN74LVC112A is a high-drive CMOS device that can be used for a multitude of bus interface type applications

where the data needs to be retained or latched. It can produce 24 mA of drive current at 3.3 V, making it Ideal for

driving multiple outputs and good for high-speed applications up to 150 MHz. The inputs are 5.5-V tolerant

10.2 Typical Application

Figure 5. Typical Application Schematic

10.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus

contention because it can drive currents that would exceed maximum limits. The high drive will also create fast

edges into light loads, so routing and load conditions should be considered to prevent ringing.

10.2.2 Detailed Design Procedure

1. Recommended Input Conditions

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For rise time and fall time specifications, see

Δt/ΔV in the Recommended Operating Conditions table.

–

–

2. Recommend Output Conditions

–

Load currents should not exceed 50 mA per output and 100 mA total for the part.

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10

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