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PI4MSD5V9542AWEX Datasheet(PDF) 8 Page - Pericom Semiconductor Corporation |
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PI4MSD5V9542AWEX Datasheet(HTML) 8 Page - Pericom Semiconductor Corporation |
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8 / 13 page ![]() ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2015-07-0033 PT0523-4 8/18/15 8 PI4MSD5V9542A 2 Channel I2C bus Multiplexer with Interrupt Logic Interrupt handling The PI4MSD5V9542A provides 2 interrupt inputs, one for each channel and one open-drain interrupt output. When an interrupt is generated by any device, it will be detected by the PI4MSD5V9542A and the interrupt output will be driven LOW. The channel need not be active for detection of the interrupt. A bit is also set in the control byte. Bits 5:4 of the control byte correspond to channel 1, channel 0 of the PI4MSD5V9542A, respectively. Therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0 would cause bit 4 of the control register to be set on the read. The master can then address the PI4MSD5V9542A and read the contents of the control byte to determine which channel contains the device generating the interrupt. The master can then reconfigure the PI4MSD5V9542A to select this channel, and locate the device generating the interrupt and clear it. It should be noted that more than one device can be providing an interrupt on a channel, so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt. The interrupt inputs may be used as general purpose inputs if the interrupt function is not required.If unused, interrupt input(s) must be connected to VCC through a pull-up resistor. D7 D6 INT1 INT0 D3 B2 B1 B0 Command 0 0 X 0 X X X X no interrupt on channel 0 1 interrupt on channel 0 0 0 0 X X X X X no interrupt on channel 1 1 interrupt on channel 1 Control register read — interrupt Power-on reset When power is applied to VCC, an internal Power-On Reset (POR) holds the PI4MSD5V9542A in a reset condition until VCC has reached VPOR. At this point, the reset condition is released and the PI4MSD5V9542A registers and I2C-bus state machine are initialized to their default states (all zeroes), causing all the channels to be deselected. Thereafter, VCC must be lowered below 0.2 V for at least 5 us in order to reset the device. |
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