TAS5709APHPR datasheet(19/61 Pages) TI1

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2C COMPATIBLE SERIAL CONTROL INTERFACE

SERIAL INTERFACE CONTROL AND TIMING

I2S Timing

SCLK

32Clks

LRCLK(NoteReversedPhase)

LeftChannel

24-BitMode

20-BitMode

16-BitMode

MSB

LSB

32Clks

RightChannel

2-ChannelI S(PhilipsFormat)StereoInput

T0034-01

MSB

LSB

SCLK

TAS5709, TAS5709A

www.ti.com ..................................................................................................................................... SLOS599A – NOVEMBER 2008 – REVISED SEPTEMBER 2009

Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.

For a detailed description of using audio processing features like DRC, EQ, 3D, and bass boost, see the User's

Guide and TAS570X GDE software development tool documentation. Also see the GDE software development

tool for the device data path.

The TAS5709 DAP has an I2C serial control slave interface to receive commands from a system controller. The

serial control interface supports both normal-speed (100-kHz) and high-speed (400-kHz) operations without wait

states. As an added feature, this interface operates even if MCLK is absent.

The serial control interface supports both single-byte and multiple-byte read and write operations for status

registers and the general control registers associated with the PWM.

I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the

right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or

64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes

state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge of the

bit clock. The DAP masks unused trailing data-bit positions.

NOTE: All data presented in 2s-complement form with MSB first.

Figure 17. I2S 64-fS Format

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